Patent Number 4896262 Issue Date 1990 01 23 Appl. Data 704520 1985 02 22 Assignee Kabushiki Kaisha Meidensha Inventor(s) Wayama, Yukio Miyajima, Naoto Shinozaki, Michio Yashima, Kazunari State/Country JPX Title Emulation device for converting magnetic disc memory mode signal from computer into semiconductor memory access mode signal for semiconductor memory Abstract A semiconductor backing storage device is connected to a computer system accessible only in magnetic disc access mode for improvement in access time. In transferring information data between the computers and the semiconductor backing storage device, access control command signals peculiar to magnetic disc access mode are all disregarded and address data peculiar to magnetic disc access mode are converted into those necessary for semiconductor memory mode in writing or reading information data. To further decrease access time, one-word buffers are provided for a semiconductor backing storage controller and the backing storage device, so that the preceding data are transferred from the buffers while the current data are transferred to the buffers after necessary processing. The semiconductor backing storage memory is also usable for a multicomputer system by providing cross-call function for the semiconductor backing storage controller. U.S. Class 395/500 364/DIG1 364/221.2 364/228.1 364/232.8 364/232.9 364/236.2 364/238.4 364/240 364/243 364/243.4 364/247 364/248.1 364/249 364/264.3 364/265 IPC G06F 3/05 G06F 5/00 G06F 13/00 U.S. Refs 4136386 4148098 4159534 4210959 4215400 4295205 4338644 4399503 4456971 4467421 Priority JPX 19840224 59-33798 JPX 19840224 59-33801 JPX 19840224 59-33802 Patent Number 4899273 Issue Date 1990 02 06 Appl. Data 940539 1986 12 10 Assignee Hitachi, Ltd. Inventor(s) Omoda, Koichiro Miyamoto, Shunsuke Nakagawa, Takayuki Takamine, Yoshio Nagashima, Shigeo Miyoshi, Masayuki Kazama, Yoshiharu Kinoshita, Yoshiaki State/Country JPX Title Circuit simulation method with clock event suppression for debugging LSI circuits Abstract A computer implemented logic simulation method, for inspecting logical operations of large scale logic circuits, computes a variation of an output of at least one latch in a clock synchronized logic circuit. The clock-synchronized logic circuit contains a combination logic circuit and a plurality of logic gates. Each of the logic gates have at least one input signal and several other inputs connected to clocking signal sources of different phases. The latch is activated by the rise or fall of the clock signals for holding the output from the combination logic circuit. The method thus implements sampling instants of the output for ascertaining the logical operations of the large scale circuits. U.S. Class 395/500 364/DIG1 364/221 364/221.2 364/221.7 364/231.8 364/232.21 364/232.3 364/247 364/264 364/264.3 364/265 364/266 364/267 364/267.2 364/267.4 364/267.91 364/270 364/270.1 364/270.2 364/270.3 364/271 364/271.5 364/285 371/23 IPC G06F 9/44 G06F 11/22 G06F 11/26 U.S. Refs 3932843 3961250 4306286 4342093 4635218 4654851 4713606 4747102 Priority JPX 19851211 60-276761 Patent Number 4899274 Issue Date 1990 02 06 Appl. Data 348143 1989 05 02 Assignee International Business Machines Corporation Inventor(s) Hansen, Barry W. Romon, Raymond F. State/Country MN Title Dynamic terminal address allocation by the terminal itself in a data processing system Abstract A system has a central processor and multiple addressable terminals connected by a communication cable. The terminal itself contains a list of candidate addresses it can use. The terminal determines which of the candidate addresses are already in use by other terminals, and selects one (or more) for itself that is not in use. U.S. Class 395/200 364/DIG1 364/228.3 364/228.4 364/229 364/229.2 364/232.3 364/240.8 364/241.9 364/243 364/243.2 364/248.1 364/256.8 364/266.5 364/280 364/281.3 395/500 IPC G06F 7/00 U.S. Refs 4025903 4403303 4488232 4511958 4551721 4591973 4638313 4644468 4644470 Related Data This is a continuation of copending application Ser. No. 789,798 filed on Oct. 21, 1985, now abandoned. Patent Number 4899306 Issue Date 1990 02 06 Appl. Data 769138 1985 08 26 Assignee American Telephone and Telegraph Company, AT&T Bell Laboratories Inventor(s) Greer, Steven C. State/Country IL Title Test interface circuit which generates different interface control signals for different target computers responding to control signals from host computer Abstract A general purpose computer test interface is used to test various types of computers having differing input/output characteristics. The interface comprises a control unit which is responsive to messages from a controlling host computer to generate a unique set of type control signals for each computer type to be tested. Interfce control logic circuits combine the type control signals with bus control signals from a target computer under test to adapt the interface for communication with each of the different types of targets defined by the type control signals. U.S. Class 395/500 364/DIG2 364/916.4 364/927.92 364/927.98 364/927.99 364/940 364/940.81 364/941 364/942 364/946.7 364/947 364/947.2 364/948.1 364/949.4 364/965 364/965.4 371/16.1 371/22.2 IPC G06F 15/20 G06F 9/06 U.S. Refs 3846763 4057847 4069510 4127896 4195258 4231087 4315310 4317199 4402055 4485439 4606025 4654781 Patent Number 4914569 Issue Date 1990 04 03 Appl. Data 115146 1987 10 30 Assignee International Business Machines Corporation Inventor(s) Levine, Frank E. Mohan, Chandrasekaran State/Country TX Title Method for concurrent record access, insertion, deletion and alteration using an index tree Abstract A method for fetching key record data in a group or record keys according to at least a portion of a key record through an index tree is provided. The index tree provides concurrent accesses of record keys by different transactions. The index tree includes a root node connected to at least one level of nodes, each node having a key record reference to one of more nodes in a next successive level and having bottom nodes that provide access to the key data. The method consists of the steps of (1) traversing across said nodes from said root node by using said key record portion until a bottom node is reached; (2) limiting all but read accesses to the node being traversed and a previously accessed node, to other concurrent transactions; (3) identifying said key record in said bottom node; (4) limiting all but read accesses to said key record; (5) removing all access limitations to traversed nodes; (6) fetching key record data; and (7) removing the access limitation to the key record after the record data has been fetched. Further, methods for inserting and deleting record keys are provided. Additionally, a method for changing the index tree structure while allowing concurrent accesses to take place is provided. U.S. Class 395/500 364/DIG1 364/222.81 364/222.82 364/246.6 364/246.8 364/251 364/251.6 364/252.3 364/252.4 364/252.6 364/281.3 364/281.4 364/282.1 364/282.2 364/283.4 IPC G06F 15/40 U.S. Refs 4604694 4606002 4627019 4677550 4698752 Other Refs "Efficient Locking for Concurrent Operations on B-Trees", ACM Transactions on Database Systems, vol. 6, No. 4, Dec., 1981, pp. 650-670. "Ubiquitous B-Tree", Computer Surveys, vol. 11, No. 2, Jun., 1979, pp. 121-137. "Concurrent Operations on B-Trees with Overtaking", by Sagiv ACM Sigact-Sigmond Symposium on Principles of Database System, Mar., 1985, pp. 28-37. "Index Locking and Splitting", IBM Technical Disclosure Bulletin, vol. 25, No. 7B, Dec., 1985, pp. 3725-3927. "Locking Protocol for Concurrent Operations on B-Trees", IBM Technical Disclosure Bulletin, vol. 19, No. 10, Mar., 1977, pp. 3887-3889. Data Structure and Algorithms, by Aho, Hopcroft and Ullman, Addison-Wesley Publishing Company, 1983, pp. 170-179. "Multilevel Locking with Deadlock Avoidance", IBM Technical Disclosure Bulletin, vol. 21, No. 4, Sep., 1987, pp. 1723-1728. "Locking Technique in a Relational Data Base: Locking on Intents", IBM Technical Disclosure Bulletin, vol. 18, No. 7, Dec., 1975, pp. 2324-2326. "Index Mini-Pages", IBM Technical Disclosure Bulletin, vol. 25, No. 11A, Apr., 1983, pp. 5460-5463. "Locking Mechanism for Controlling Access to Data Base Resources", IBM Technical Disclosure Bulletin, vol. 29, No. 3, Aug., 1986, pp. 1193-1195. "Multi-Access Data Sharing Facility Utilizing Magnetic Bubble Storage", IBM Technical Disclosure Bulletin, vol. 23, No. 8, Jan., 1981, pp. 3882-3885. "Integrated Concurrency and Shared Buffer Coherency Control for Multi-Systems", IBM Technical Disclosure Bulletin, vol. 28, No. 10, Mar., 1986, pp. 4642-4650. "Copy Currency Control in Distributed Data Networks", IBM Technical Disclosure Bulletin, vol. 24, No. 5, Oct., 1981, pp. 2348-2351. "Performance Without Deadlock Algorithm", IBM Technical Disclosure Bulletin, vol. 22, No. 10, Mar., 1980, p. 6759. "Sharing of Disk Files Without Locking", IBM Technical Disclosure Bulletin, vol. 22, No. 7, Dec., 1979, pp. 2887-2889. "Hardware-Supported Critical Sections to Minimize Process Waiting/Dispatching", IBM Technical Disclosure Bulletin, vol. 22, No. 3, Aug., 1979, pp. 1290-1293. "Spin Queues", IBM Technical Disclosure Bulletin, vol. 18, No. 6, Nov., 1975, pp. 1953-1954. "Locking Architecture in a Multiple Virtual Memory Multi-Processing System", IBM Technical Disclosure Bulletin, vol. 16, No. 7, Dec. 1973. "Transaction Monitoring in Encompass (TM): Reliable Distributed Transaction Processing", by Borr, Procedures International Conference on Very Large Data Bases, Sep., 1981, pp. 244-254. "Robustness to Crash in a Distributed Database: A Non Shared-Memory Multi-Processor Approach", by Borr, Proceedings 10th International Conference on Very Large Databases, Singapore, Aug., 1984. "The Recovery Manager of the System R Database Manager", ACM Computing Surveys, vol. 13, No. 2, Jun., 1981, pp. 223-242. Patent Number 4914585 Issue Date 1990 04 03 Appl. Data 197795 1988 05 23 Assignee Hewlett-Packard Company Inventor(s) Packard, Barbara B. Stearns, Glenn Watson, Ralph T. State/Country CA Title Modular complier with a class independent parser and a plurality of class dependent parsers Abstract A modular compiler is used to compile code for execution by an agent engine and a plurality of application programs. The modular compiler includes a class independent compiler which parses program code which is to be executed by the agent engine. The modular compiler also includes a class dependent parser for each application program. Each class dependent parser parses program code which is to be executed by its respective application program. When an application program is added to the computing system, an associated class dependent parser is added to the modular compiler. When an application program is removed from the computing system, the associated class dependent parser is removed from the modular compiler. U.S. Class 395/500 364/DIG1 364/228 364/228.4 364/236.8 364/241.9 364/280 364/280.4 364/281.3 364/281.7 364/282.1 364/283.1 364/286 364/286.3 IPC G06F 9/00 U.S. Refs 4787035 Patent Number 4914616 Issue Date 1990 04 03 Appl. Data 131864 1987 12 11 Assignee Mitsubishi Denki Kabushiki Kaisha Inventor(s) Shiraishi, Taketora Shimazu, Yukihiko State/Country JPX Title Coded incrementer having minimal carry propagation delay Abstract As the incrementer of the invention comprises a shift register for its lower order bits, while its higher bit portions are constructed in the same way as a conventional incrementer, the incrementer can give output signals directly to a memory and the like without the necessity of decoding the same, and the incrementer is free from carry propagation delay possibilities, which assures an improved rate of operation of the incrementer as a whole. U.S. Class 364/770 364/DIG2 364/925.6 364/926.5 364/933.2 364/933.5 364/933.9 364/934 364/934.1 364/937.1 364/942.8 364/946.2 364/947.6 364/947.7 364/950 364/950.2 364/950.4 364/960.2 364/960.6 364/965 364/965.5 377/44 377/46 377/54 377/78 377/126 395/500 IPC G06F 7/50 U.S. Refs 3081031 3393298 3411094 3673390 3838399 3891973 3894635 4075464 4084082 4218750 4241410 4256954 4519091 4530108 Foreign Refs JPX 198507 0139025 Other Refs G. Williams--"Digital Technology", Science Research Associates--1977, 1982--pp. 283-285. Computer System Architecture, pp. 54-59, M. Morris Mano, 1982, Prentice-Hall, Inc. Priority JPX 19861215 61-298007 Patent Number 4918594 Issue Date 1990 04 17 Appl. Data 011068 1987 02 04 Assignee Hitachi, Ltd. Inventor(s) Onizuka, Nobuhiko State/Country JPX Title Method and system for logical simulation of information processing system including logic circuit model and logic function model Abstract A logical simulation system for a data processor includes a logic circuit model constituting a part of logic of the data processor to be tested with basic logic elements capable of calculating operation processes in detail, a logic function model describing functional operations of the other logic of the data processor in terms of machine word instructions for executing functional operations of the other logic at a high speed, and a communication routine for performing data transfer between both the models and controlling the execution of instructions. The processings for executing individual instructions contained in a test program are shared between both the models through the medium of the communication routine. U.S. Class 395/500 364/DIG1 364/221.2 364/221.7 364/221.9 364/222.2 364/222.82 364/232.3 364/232.8 364/237.2 364/238.6 364/241.2 364/247 364/259 364/259.9 364/260 364/261 364/262.4 364/263 364/263.2 364/264 364/270 364/274.1 364/488 364/578 IPC G06F 15/00 G06F 9/00 U.S. Refs 4342093 4527249 4628471 4635218 4656580 4713606 4725975 4763289 4782440 Foreign Refs EPX 198511 0160944 JPX 198408 59-148971 (A) JPX 198408 59-151247 (A) JPX 198411 59-195751 (A) JPX 198505 60-91455 JPX 198512 60-254351 Other Refs Zwolinski et al, "The Design of an Hierarchical Circuit-Level Simulator", Electronic Design Automation (EDA 84), Conference Publication No. 232, pp. 9-12, Mar. 1984. Priority JPX 19860207 61-23782 Patent Number 4918602 Issue Date 1990 04 17 Appl. Data 073815 1987 07 15 Assignee Computer Associates International, Inc. Inventor(s) Bone, William K. Giannini, John M. State/Country IL Title Data processing system and method Abstract A system and method are disclosed for computer implementation of a plurality of diverse commercial functions, the system comprising a central processing unit (CPU), a first plurality of storage modules each individually addressable by the CPU and containing what is termed a "component subprocess", and a second plurality of storage modules, each also individually addressable by the CPU and containing what is termed a "log point". Planner interactive means are provided and furnished by the CPU from further storage of the system with menus for the planning of what are termed system "products". Such menus present for selection various components which can be implemented. Responsively to planner component selection, for each component selected by the planner, the CPU responds by displaying the component processes associated with such component and the planner accumulates desired products by selecting component processes. Again from system storage, the CPU furnishes, for display and selection, system log points, which are predefined conditions in a component process which collect transaction information. In providing products for use, the CPU obtains log points and component subprocess from storage in sequences according with the component processes of the products. U.S. Class 364/401 395/500 IPC G06F 9/00 U.S. Refs 3654616 4607327 4656603 4663704 4683549 4700290 4750105 Patent Number 4920481 Issue Date 1990 04 24 Appl. Data 130369 1987 12 08 Assignee Xerox Corporation Inventor(s) Binkley, Joseph H. Caro, Perry A. Dillon, John B. Fay, Charles R. Gibbons, Jonathan Hooks, Hilary N. Kadifa, Abdo G. Lee, Jeffery W. Lynch, William C. Mock, Clayton W. Neely, Everett T. Tallan, Michael L. Thompson, Geoffrey O. Vukkadala, Gaya Wick, John D. Woods, Donald R. State/Country CA Title Emulation with display update trapping Abstract An emulating data processor includes a host system and an emulating processor with outputs to and inputs from the host system. The emulating processor executes sequences of instructions executable by a PC being emulated, but a host processor independently executes sequences of its instructions which are different from PC instructions. Circuitry monitors the emulating processor outputs and provides information to the host system so that it can emulate the environment of the PC CPU, emulating both memory and I/O devices. The memory accesses of the emulating processor are mapped into the host system memory, so that the host processor is protected from defective PC software on the emulating processor. The display updates of the emulating processor are detected and provide information for the host processor in updating a part of its display which provides the information a PC display would provide simultaneously with the display characteristic of the host system. An input/output processor handles I/O operation requests of the emulating processor, using the host system I/O devices to emulate some of the PC I/O devices. The host system emulates the environment of the emulating processor while emulating the user interface of the PC. U.S. Class 395/500 364/DIG1 364/221 364/221.2 364/221.7 364/228 364/228.6 364/232.3 364/261.6 364/269.4 IPC G06F 15/16 G06F 3/153 U.S. Refs 3932843 3955180 4031517 4042914 4253145 4315310 4365295 4456954 4458331 4463442 4484266 4564903 4590556 4591975 4621319 4648034 4665482 4695945 4703420 4709328 4716526 4722048 4727480 4729094 4757441 4787026 4833596 Foreign Refs EPX 198512 0165517 EPX 198601 0168034 EPX 198610 0197499 EPX 198612 0205949 EPX 198702 0210345 EPX 198707 0229336 EPX 198707 0229700 Other Refs Interface Age, Sep. 1984, pp. 79-81. Interface Age, May 1984, pp. 100-107. Mark Heck, "Quadlink, Running Apple Software on an IBM PC", Interface Age, May 1984, pp. 108-110. Robert Moskowitz, "Appli-Card Enhancing Your Apple", Interface Age, Aug. 1983, pp. 107, 108, 111. Robert Peck, "Expanding Your Apple's Applications", Byte, Dec. 1984, pp. A45-A47, A122-126. David Morganstein, "ALF's 8088 Coprocessor for Your Apple", Byte, Dec. 1984, pp. A38, 40-43. Libertine, J. A., "The Xerox 16/8 Professional: A Workhorse for the Office", Business Computer Systems, May 1984, pp. 147, 149, 151. Xerox Corporation, "16/8 Professional Computer", one sheet brochure. Honeywell Information Systems Inc., "microSystem 6/10", 1985. Xerox Corporation, "Xerox 16/8 Professional Computer--Two Computers in One--Meeting Leaders Guide", pp. 1-11, 1983. Deitel, Harvey M., "An Introduction to Operating Systems", Addison-Wesley Publishing Company, Inc., Revised First Edition, Jul. 1984, pp. 601-629. Krishnamurty, R. and Mothersole T., "Coprocessor Software Support", IBM Personal Computer Technology, IBM, Austin, 1986, pp. 142-146. Goering, R., "Apollo Entry Fuels CAAE/CAD Workstation Battle", Computer Design, Mar. 1, 1986, pp. 26-27. Rose, C. D., "Apollo Fights Back with New Work Stations", Electronics, Feb. 24, 1986, pp. 20-21. Hall, Dennis E., et al., "A Virtual Operating System", Communications of the ACM, vol. 23, No. 9, Sep. 1980, pp. 495-502. Madnick, Stuart E. et al., "Operating Systems", McGraw-Hill Book Company, 1974, pp. 549-563. Mace, S. and Sorension, K., "Amiga, Atari Ready PC Emulators", InfoWorld, vol. 8, No. 18, May 5, 1986. "IBM Introduces High-Speed Personal of Multi-User Workstations with New Technology for Technical Professionals", Business Wire Inc., Jan. 1986. Irwin J. W., "Use of a Coprocessor for Emulating the PC AT", IBM Personal Computer Technology, IBM Austin, 1986, pp. 137-141. Related Data This is a division of application Ser. No. 856,526, filed Apr. 28, 1986. Patent Number 4924327 Issue Date 1990 05 08 Appl. Data 393134 1989 08 14 Assignee NeXT, Inc. Inventor(s) Seamons, John K. Grundy, Kevin P. State/Country CA Title System and method for improving the performance of high-density data storage media Abstract In a computer system equipped with a magneto-optical disk drive having high data density, and therefore lengthy format times, and also requiring an erase step before each write operation, a system and method for decreasing user waiting time is provided. The system and method format the disk on a continuous basis during "disk-idle" periods rather than all at once. The system and method also erase disk portions belonging to deleted data in advance during disk-idle periods, so they are ready for the next write operation. U.S. Class 360/48 364/DIG1 364/242.3 364/242.31 364/242.34 364/248.1 364/249.4 364/249.7 364/263.3 395/500 IPC G11B 5/09 Other Refs Peter Norton's Inside OS/2 by R. Latore et al, Brady Books .COPYRGT. 1988, (pp. 10 & 11). IBM OS/2 S.E. License Information, (p. 2). R. P. Freese, "Optical disks become erasable", IEEE Spectrum, Feb. 1988, pp. 41-45. Related Data This is a division of application Ser. No. 255,337 filed Oct. 11, 1989. Patent Number 4924384 Issue Date 1990 05 08 Appl. Data 247794 1988 09 21 Assignee International Business Machines Corporation Inventor(s) Hao, Ming C. Obermarck, Ronald L. Trivett, Gene E. Trivett, Lynn State/Country CA Title Method for controlling the peer-to-peer processing of a distributed application across a synchronous request/response interface using push-down stack automata Abstract A method for coordinating recursive requests and responses in the peer-to-peer processing of a distributed application across a synchronous request/response interface. The method utilizes, on each side of the interface, a decision table and a local LIFO stack of generated and received requests, responses, and input from the application. The local stack is run in a push-pop manner and assists the local decision table in conducting the peer-to-peer processing until the LIFO stack becomes exhausted. A fault on either side of the interface results in undoing the processing by unwinding each stack back to a predetermined point. If one side operates as a persistent server, its application program environment is saved from one request to another by a dynamic save and simulated return to the application. Lastly, a request/demand is substituted for a demand/request by the server so as to change the server and requester roles of either side of the interface. U.S. Class 395/500 364/244 364/244.6 364/280 364/280.6 395/325 IPC G06F 15/16 U.S. Refs 4410940 4430699 4736321 4819159 Other Refs Tenenbaum and Augenstein, "Data Structures Using PASCAL", copyright 1986, by Prentice-Hall, Inc. pp. 67-83. Patent Number 4924429 Issue Date 1990 05 08 Appl. Data 159741 1988 02 24 Assignee NEC Corporation Inventor(s) Kurashita, Masahiro Nomizu, Nobuyoshi State/Country JPX Title Hardware logic simulator Abstract A hardware logic simulator includes a first memory, having memory locations respectively corresponding to a plurality of signals in a logic circuit to be simulated, for storing data representing states of the plurality of signals, and a second memory having memory locations respectively corresponding to those of the first memory and an address bus common therewith. When the content of a memory location at a given address of the first memory is changed during simulation, data representing the change in state of the corresponding signal is written in a second memory location corresponding to the given address. The content of the second memory is read out at the end of the simulation and the degree of completeness of the simulation is evaluated. U.S. Class 364/578 364/DIG1 364/DIG2 364/221 364/221.2 364/232.3 364/274 364/276.5 364/916 364/916.3 364/933.8 371/23 395/500 IPC G06F 9/44 G06F 12/00 G01R 31/28 U.S. Refs 4697241 4725970 4736338 4782440 4787061 Foreign Refs DEX 198401 216340 JPX 198502 61-184471 Other Refs Takasaki et al., "HAL II: A Mixed Level Hardware Simulation System," 1986, IEEE 23rd Design Automation Conference, pp. 581-587. Priority JPX 19870225 62-40343 JPX 19870423 62-100287 Patent Number 4926322 Issue Date 1990 05 15 Appl. Data 081325 1987 08 03 Assignee Compag Computer Corporation Inventor(s) Stimac, Gary A. Crosswy, William C. Preston, Stephen B. Flannigan, James S. State/Country TX Title Software emulation of bank-switched memory using a virtual DOS monitor and paged memory management Abstract A virtual DOS monitor uses the paging hardware of a processor such as the Intel 80386 microprocessor in conjunction with its Virtual-8086 mode of operation to emulate expanded memory using extended memory. Support for application programs which access expanded memory is thereby provided without the need for additional memory boards or other hardware. U.S. Class 395/500 364/DIG1 364/228.2 364/230.2 364/232.1 364/232.3 364/243 364/245 364/245.31 364/246.3 364/280.8 364/282.2 IPC G06F 9/00 G06F 13/00 G06F 11/30 U.S. Refs 4279014 4285039 4285040 4403283 4439762 4449181 4449184 4481570 4503491 4520453 4545010 4601018 4609996 4615006 4707803 4723205 4727480 4727485 4742450 4744048 4747040 4777589 4779187 4831522 4849875 Other Refs Randall L. Hyde, "Overview of Memory Management", Byte Apr. 88, pp. 219-225. Carl Hensler & Ken Sarno, "Marrying Unix and the 80836", Byte Apr. 88, pp. 237-244. Patent Number 4928237 Issue Date 1990 05 22 Appl. Data 030789 1987 03 27 Assignee International Business Machines Corp. Inventor(s) Bealkowski, Richard Dayan, Richard A. Doria, David J. Kinnear, Scott G. Krantz, Jeffrey I. Liverman, Robert B. Sotomayor, Guy G. Williams, Donald D. Vaiskauckas, Gary A. State/Country FL Title Computer system having mode independent addressing Abstract A computer system and method for operating a computer system capable of running in mutually incompatible real and protected addressing modes, in which programs written for one mode can be run in the other mode without modification. The operating system using BIOS assembles two different common data areas for the two modes, each inclusive of device block pointers, function transfer table pointers, data pointers, and function pointers. The common data area for the real mode is assembled first. To assemble the pointers for the protected mode common data area, the offset values from the real mode area are copied directly, and then selector values are inserted whose physical addresses correspond to the segments of the corresponding pointers in the real mode area. The selector values are derived from a segment descriptor table. U.S. Class 395/500 364/DIG1 364/231 364/232.9 364/244.6 364/254.8 364/255.1 364/255.5 364/255.7 364/256.3 364/256.4 364/280 364/280.2 364/280.9 395/700 IPC G06F 9/00 U.S. Refs 4004278 4084224 4128875 4270167 4296468 4315321 4442484 4514805 4727480 4736290 4747040 4779187 4825358 4849875 Foreign Refs EPX 198610 0197552 EPX 198612 0208429 Other Refs Childs, Jr., et al.; "A Processor Family for Personal Computers"; 1984. Intel iAPX 286 Operating Systems Writer's Guide, Intel Corporation, 1983. Intel iAPX 286 Programmer's Reference Manual, Intel Corporation, 1983. Patent Number 4931923 Issue Date 1990 06 05 Appl. Data 025499 1987 03 13 Assignee Apple Computer, Inc. Inventor(s) Fitch, Jonathan Hochsprung, Ronald State/Country CA Title Computer system for automatically reconfigurating memory space to avoid overlaps of memory reserved for expansion slots Abstract A personal computer system includes a main circuit board having a central processing unit and expansion slots each of which is adapted to receive a printed circuit board card. The main circuit board further includes memory, a 32-bit address bus with control signals associated therewith, and input/output circuitry. The slot is coupled to the 32-bit address bus, which is substantially a NUBUS bus, and the slot includes distinct identification line means which provide the slot with an identification number (distinct number) in the computer system. The computer system reserves 256-megabytes of memory space ranging from location $X000 0000 to location $XFFF FFFF for memory on a card in a slot having a distinct number equal to $X. U.S. Class 395/500 364/DIG1 364/232.7 364/232.8 364/238 364/238.3 364/238.4 364/240 364/245 364/245.2 364/245.31 IPC G06F 9/02 G06F 9/06 G06F 13/00 G06F 13/10 U.S. Refs 3675083 3710324 3993981 4000485 4250563 4368514 4467436 4633402 Foreign Refs DEX 197501 1380776 GBX 198105 2060961 GBX 198301 2101370 GBX 198302 2103397 Patent Number 4931924 Issue Date 1990 06 05 Appl. Data 133805 1987 12 16 Assignee Hitachi, Ltd. Inventor(s) Kageura, Kenichi State/Country JPX Title Data transfer speed control apparatus capable of varying speed of data transfer between devices having different transfer speeds Abstract A data transfer speed control apparatus for effecting data transfer between semiconductor storage devices and CPU channel devices having maximum transfer speeds different from each other has connection line setting sections indicating the maximum transfer speeds of the semiconductor storage devices and the CPU channel devices. When data transfer between one of the semiconductor storage devices and one of the channel devices is to be made, a transfer speed determining section determines an actual speed of data transfer between the one semiconductor storage device and the one channel device on the basis of the indicated maximum transfer speeds of the one semiconductor storage device and the one channel device to be that one of both the maximum transfer speeds which is lower. The transfer speed of the semiconductor storage device and the channel device is set to the transfer speed determined by the transfer speed determining section. U.S. Class 395/500 364/DIG1 364/228.1 364/238.4 364/239 364/239.1 364/241.9 364/243 364/249 364/260 364/260.1 IPC G06F 5/06 G06F 3/00 U.S. Refs 3937938 3980993 4344132 Other Refs Microprocessor Interfacing, 1982-Prof. Andrew C. Staugaard, Jr. Priority JPX 19861219 61-301817 Patent Number 4937036 Issue Date 1990 06 26 Appl. Data 170959 1988 03 21 Assignee Xerox Corporation Inventor(s) Beard, Marian H. Caro, Perry A. Hsiao, Jennifer B. Mackey, Kevin J. Sandman, Jr., James G. Steinbach, Gary R. Woods, Donald R. State/Country CA Title Concurrent display of data from two different display processors and user interface therefore Abstract A multiprocessor system comprises concurrent display of video data reflecting the operation of two processors in discrete portions of a single display screen with a user interface adapted for interaction with both processors. One processor controls the entire display while allocating a portion of the display screen for the use of the other processor which processor emulates a target processor system, for example, the IBM PC. To fully emulate another target processor system requires emulation of its screen facility and abstractions used in the display operations of the targeted system. The one processor is a general purpose host computer system having a central processor with real resources including I/O devices, main memory, a video display for displaying information on the display screen of the display and user input means, e.g. a keyboard and a mouse, to the host computer to provide input to the display screen. Also included in the system is at least one emulating computer having a processor emulating the target processor unit with interface means for emulating the previously identified real resources for the emulating processor including means in the host system responsive to the input/output of the emulating processor for sharing of the central processor real resources by the emulating processor. U.S. Class 340/706 340/709 364/DIG1 364/DIG2 364/228.1 364/228.4 364/228.5 364/230.4 364/232.3 364/234 364/236.8 364/237.2 364/237.3 364/262.4 364/927.2 364/927.63 364/927.631 364/927.81 364/931 364/931.4 364/931.5 364/978 364/978.1 395/500 IPC G09G 1/00 U.S. Refs 3643252 3932843 4149148 4149238 4204206 4253145 4278973 4315310 4365295 4437184 4456954 4458331 4463442 4484266 4484302 4550386 4555775 4564903 4574364 4621319 4757441 4787026 Foreign Refs EPX 198601 0168034 DEX 198705 0223383 Other Refs Goering, R., "Apollo Entry Fuels CAE/CAD Workstation Battle", Computer Design, Mar. 1, 1986, pp. 26-27. Rose, C. D., "Apollo Fights Back With New Work Stations", Electronics, Feb., pp. 20-21. Mace, S. and Sorenson, K., "Amiga, Atari Ready PC Emulators", Info World, vol. 8, No. 18, May 5, 1986. 8010 Star Information System Reference Library, 5.0 Update, Xerox Corporation, 1984, pp. 119-188. David C. Smith et al, "The Star User Interface: An Overview", Proceedings of the National Computer Conference, Houston, Tex., Jun. 7-10, 1982, pp. 515-528. David C. Smith et al, "Designing the Star User Interface", Byte Magazine, vol. 7(4), 15-28, Apr. 1982. Irwin, J. W., "Use of a Coprocessor for Emulating the PC AT", in F. Waters, Ed., IBM RT Personal Computer Technology, IBM, Austin, 1986, pp. 137-141. Krishnamurty, R., and Mothersole, T., "Coprocessor Software Support", in F. Waters, Ed., IBM RT Personal Computer Technology, IBM, Austin, 1986, pp. 142-146. "Copydisk", Xerox Corp., Palo Alto, 1980. Related Data This is a division, of application Ser. No. 856,525, filed Apr. 28, 1986. Patent Number 4937770 Issue Date 1990 06 26 Appl. Data 292620 1988 12 29 Assignee Teradyne, Inc. Inventor(s) Samuels, Michael W. Zasio, John J. State/Country CA Title Simulation system Abstract A levelized simulation system includes a means for storing a model of a logic system to be simulated. The logic system has a plurality of levels of logic which are synchronously clocked. A processing system including an arithmetic logic unit sequentially tests each element of said logic system, one level of logic at a time, thus each logic element in the first level is tested with the results there stored in a state memory, after which the logic elements of the second level of the logic system are tested and so on. During each test a comparison is made to determine whether there is a defect in the logic design. U.S. Class 364/578 364/DIG2 364/490 364/916.3 364/928.4 364/933.8 364/944.9 364/950.3 364/965.2 365/189.05 365/230.08 371/23 395/500 IPC G06G 7/48 G11C 7/00 U.S. Refs 2488740 3551891 3702003 3934231 3961250 4017840 4051353 4055851 4140921 4236203 4293919 4306286 4365334 4404635 4424581 4428060 4445172 4450560 4451880 4472804 4482953 4527249 4541071 4584642 4590581 4628471 4663741 4725975 4736338 4744084 4755933 4782440 4825416 4845667 4849937 Foreign Refs EPX 198401 0099114 FRX 198602 2568698 JPX 198110 0134390 Other Refs Hwang, Kai et al., Computer Architecture and Parallel Processing, McGraw-Hill, 1984, pp. 145-154, 164-170. Barto et al., "A Computer Architecture for Digital Logic Simulation", Electronic Engineering, Sep. 1980, vol. 52, No. 643, pp. 35-66. Lineback, J. Robert, "Logic Simulation Speeded with Special Hardware", Electronics Review, Jun. 16, 1982, vol. 55, No. 12, pp. 45-46. Agnus R. McKay, "Comment on Computer-Aided Design Simulation of Digital Design Logic", IEEE Transactions on Computers, Sec. 1969, p. 862. Related Data This is a continuation of co-pending application Ser. No. 854,554 filed on Feb. 7, 1986 which is a continuation of application Ser. No. 826,927 filed on Feb. 7, 1986 now abandoned. Patent Number 4939507 Issue Date 1990 07 03 Appl. Data 232061 1988 08 15 Assignee Xerox Corporation Inventor(s) Beard, Marian H. Caro, Perry A. Hsiao, Jennifer B. Mackey, Kevin J. Sandman, Jr., James G. Steinbach, Gary R. Woods, Donald R. State/Country CA Title Virtual and emulated objects for use in the user interface of a display screen of a display processor Abstract A user interface is represented on the display screen in the form of metaphoric objects, called icons, with which the user can interact by changing the input focus to a designated object by visually pointed to it via the input means, which thereafter permits manipulation of the designated object or interaction with data input/output relative to the designated object. This input means is also used to initially change the input focus to either the allocated emulating processor screen portion or to the remaining portion of the central processor display screen prior to interaction with the metaphoric objects in a selected screen portion, the change of the input focus causing subsequent user input via the input means to be directed to the selected screen portion until interrupted by a change in focus input to the other of the screen portions by the user via the input means. An icon may be a representation of a virtual object, such as a virtual floppy disk, that is accessible in either the host system world or in the emulating processor world even though the virtual floppy disk may have a filing system alien to the host system world. U.S. Class 340/706 340/709 364/DIG1 364/DIG2 364/228.1 364/230.6 364/232.3 364/236.2 364/237.2 364/237.3 364/260 364/260.1 364/260.2 364/282.1 364/283.1 364/283.2 364/286 364/286.1 364/286.3 364/927.2 364/927.61 364/927.63 364/928 364/931.4 364/933.8 364/939.2 364/942.3 364/942.4 364/943 364/948.2 364/948.21 364/952 364/952.1 364/964 364/975.2 364/976 364/977 364/977.1 395/100 395/159 395/500 IPC G09G 1/00 U.S. Refs 3643252 3932843 4149148 4149238 4204206 4253145 4278973 4315310 4365295 4437184 4456954 4458331 4463442 4484266 4484302 4550386 4555775 4564903 4574364 Foreign Refs EPX 198512 0165517 EPX 198601 0168034 EPX 198705 223383 Other Refs Irwin, J. W., "Use of a Coprocessor for Emulating the PCAT", in F. Waters, Ed., IBMRT Personal Computer Technology, IBM, Austin, 1986, pp. 137-141. Krishnamurty, R., and Mothersole, T., "Coprocessor Software Support", in F. Waters, Ed., IBM RT Personal Computer Technology, IBM, Austin, 1986, pp. 142-146. "Copydisk", Xerox Corp., Palo Alto, 1980. Goering, R., "Apollo Entry Fuels CAE/CAD Workstation Battle", Computer Design, Mar. 1, 1986, pp. 26-27. Rose, C. D., "Apollo Fights Back with New Work Stations", Electronics, Feb. pp. 20-21. Mace, S. and Sorenson, K., "Amiga, Atari Ready PC Emulators", InfoWorld, vol. 8, No. 18, May 5, 1986. 8010 Star Information System Reference Library, 5.0 Update, Xerox Corporation, 1984, pp. 119-188. David C. Smith et al, "The Star User Interface: An Overview", Proceedings of the National Computer Conference, Houston, TX, Jun. 7-10, 1982, pp. 515-528. David C. Smith et al, "Designing the Star User Interface", Byte Magazine, vol. 7(4), Apr. 15-28, 1982. Related Data This is a division of application Ser. No. 06/856,525, filed Apr. 28, 1986. Patent Number 4939637 Issue Date 1990 07 03 Appl. Data 235956 1988 08 24 Assignee Metalink Corporation Inventor(s) Pawloski, Martin B. State/Country AZ Title Circuitry for producing emulation mode in single chip microcomputer Abstract An emulator circuit utilizes an Intel 8031 microprocessor with external address and data buses to emulate an Intel 8051 single chip microcomputer with no external buses by providing external registers into which the contents of the internal 8031 "Port 0" and "Port 2" registers are output and functionally "recreated". An internal emulation mode is generated in the 8031 wherein internal SFR latch contents are output to the port leads during one state and the port drivers are tri-stated to allow in-level reading of the levels of the port leads during another state. The emulator circuit generates a "Force Ports" pulse that causes the "recreated" port registers of the external circuitry to "force" external "logic" levels onto the 8031" Port 0 and Port 2 leads. U.S. Class 395/800 364/DIG1 364/231 364/232.3 364/232.8 364/232.9 364/243 364/247 364/271.6 364/271.8 395/500 IPC G06F 9/44 U.S. Refs 4441154 4514805 4527234 4677586 Related Data This application is a continuation in part of my pending application "Circuitry for Emulating Single Chip Microcomputer Without Access to Internal Busses", Ser. No. 157,104, filed Feb. 10, 1988, now U.S. Pat. No. 4,809,167, which is a continuation of Ser. No. 751,806, filed July 3, 1985, now abandoned. Patent Number 4941122 Issue Date 1990 07 10 Appl. Data 296520 1989 01 12 Assignee Recognition Equipment Incorp. Inventor(s) Weideman, William E. State/Country TX Title Neural network image processing system Abstract A neural-simulating system for an image processing system includes a plurality of networks arranged in a plurality of layers, the output signals of ones of the layers provide input signals to the others of the layers. Each of the plurality of layers include a plurality of neurons operating in parallel on the input signals to the layers. The plurality of neurons within a layer are arranged in groups. Each of the neurons within a group operates in parallel on the input signals. Each neuron within a group of neurons operates to extract a specific feature of an area of the image being processed. Each of the neurons derives output signals from the input signals representing the relative weight of the input signal applied thereto based upon a continuously differential transfer function for each function. U.S. Class 364/807 364/DIG1 364/221 364/221.1 364/221.3 364/274 364/276.5 364/276.6 364/276.8 382/15 395/11 395/22 395/24 395/500 IPC G06F 15/18 G06K 9/62 U.S. Refs 3308441 3310783 3310784 3950733 4228395 4254474 4319331 4326259 4479241 4518866 4593367 4660166 4755963 4802103 4807168 4809193 4865225 Other Refs Fukushima, K.; Miyake, S.; Ito, T., "Neocognition: A Neural Network Model for a Mechanism of Visual Pattern Recognition," IEEE Transactions On Systems, Man, and Cybernetics, vol. SMC-13, No. 5, Sep./Oct. 1983, pp. 826-834. Hecht-Nielsen, R., "Artificial Neural Systems Technology", TRW Electronic Systems Group, Jun. 9, 1986. Rumelhart, D.; Hinton, G.; Williams, R., "Learning Internal Representations By Error Propagation", Institute for Cognitive Sciences Report No. 8506, Sep. 1985. "An Introduction to Computing with Neural Nets, "R.P. Lippmann, IEEE Assp, Apr. 1987, pp. 4-21. "Self-Organizing Neural Network Models for Visual Pattern Recognition," K. Fukushima, Acta Neurochirurgica, Suppl. 41, pp. 51-67 (1987) "The Art of Adaptive Pattern Recognition by a Self-Organizing Neural Network," Carpenter et al., IEEE, Mar. 1988, pp. 77-88. "Self-Organization in a Perceptual Network," R. Linsker, IEEE, Mar. 1988, pp. 105-117. Patent Number 4942615 Issue Date 1990 07 17 Appl. Data 157958 1988 02 19 Assignee Fujitsu Limited Inventor(s) Hirose, Fumiyasu State/Country JPX Title Gate processor arrangement for simulation processor system Abstract A gate processor arrangement for a logic simulation processor system includes a new event buffer memory for storing an event at a timing t.sub.a for a predetermined logic element in a section of a logic network. A fan-out device for holding connection information for the predetermined logic element in the section of the logic network and reading the data of the predetermined logic element precedingly at a timing t is also provided. The input data of the predetermined logic element is changed at a timing "t+1". An evaluation gate buffer memory is provided having a plurality of evaluation gate memory portions able to be connected to the fan-out device and an evaluation device. The arrangement also includes a net status memory for holding net status information corresponding to input data and output data of a predetermined logic element in the section of the logic network; and an evaluation device responsive to the output of the evaluation gate buffer memory for reading the data in the net status memory, generating information for the change of the network status at a timing "t+1", and supplying the generated information to the event transmission network and/or the new event buffer memory. U.S. Class 364/578 364/DIG1 364/221 364/221.2 364/232.3 364/265 364/266.4 395/500 IPC G06F 9/44 G01R 31/28 U.S. Refs 4527249 4669083 4769817 4775950 4782440 4787061 Foreign Refs JPX 198401 59-003652 Priority JPX 19870220 62-037318 Patent Number 4945473 Issue Date 1990 07 31 Appl. Data 051084 1987 05 15 Assignee Bull HN Information Systems Inc. Inventor(s) Holtey, Thomas O. Murray, Jr., Thomas L. Smith, Scott W. Perzan, Wayne A. State/Country MA Title Communications controller interface Abstract A communications controller interface for emulating the previous system employing a plurality of line units in which data is transmitted and received. The interface includes a microprocessor-controlled interface control unit having an interface memory having a plurality of addressable storage locations. The interface memory is mapped by dividing it into a number of groups of locations corresponding to the number of communication lines with each group of locations being subdivided into further locations including a location for storage of receive data, a location for storage of transmit data, and a control location. There are a number of control elements each for generating a sequence of signals for different tasks to be performed by the interface control unit. These control elements are interconnected to the interface control unit and to the interface memory so that the multi-line communications unit is able to access different ones of the control locations for updating the status of the lines and further enabling the microprocessor-controlled interface control unit to transfer data to and from the transmit data and receive data locations of the lines in the predetermined sequence consistent with the status. U.S. Class 395/500 364/DIG1 364/222.2 364/222.3 364/232.2 364/232.3 364/238.2 364/239 364/246 364/246.3 364/247 364/247.8 395/725 IPC G06F 13/00 G06F 15/16 U.S. Refs 3651482 4433378 4482982 4488231 4546429 4628446 4724520 Patent Number 4947367 Issue Date 1990 08 07 Appl. Data 173981 1988 03 28 Assignee EMC Corporation Inventor(s) Chang, Christopher Y. Sherwin, Leo C. State/Country MA Title System for converting digital data from magnetic tape format apparatus and method for converting a sequentially accessible magnetic tape data format to directly accessible write-once disk data format to worm optical disk format Abstract Apparatus and method for storing magnetic tape format data separately stores the tape data from the tape-related information, such as file markers and interblock gap signals. The data and data-related signals are stored in separate finite length buffer memories, which when filled to a predetermined capacity are transferred to a write-once read-many (WORM) optical disk, and stored in contiguous locations beginning at one end of the addressable space on the optical disk. A separately generated tape record map list, including the WORM optical disk address of the aforementioned tape data and tape-related signals is created and stored on the optical disk in sequentially contiguous locations corresponding to sequential tape reel numbers beginning at the opposite end of the addressable space on the optical disk. The data thus recorded on the WORM optical disk is recoverable in the original magnetic tape format by recomposing the data stored in the WORM optical disk in the original magnetic tape data format. Furthermore, the conversion of data according to the present invention can be adapted to a variety of other formats to be stored to and recovered from the WORM optical disk format. U.S. Class 395/500 364/DIG2 364/927.81 364/939 364/939.2 364/952 364/952.1 364/952.31 364/952.4 364/952.6 364/960 364/963.5 395/775 IPC G06F 7/22 G06F 7/24 G06F 3/06 G06E 1/02 U.S. Refs 3573744 4000510 4084231 4089028 4229808 4238843 4321635 4321670 4355338 4467421 4511963 4541019 4575827 4578722 4701846 4727512 4775969 Other Refs "IBM DOS Version 3.10 Reference Manual", 2/85, pp. 7-19 to 7-23 and 7-157 to 7-160. Haim Brill, "Optical Storage System Emulates Formatted Tape Drive", Hard Copy, Apr '87, pp. 104-106, 108. "Optimem 1000 OEM Manual", revision 4, Apr. 1985. Patent Number 4949253 Issue Date 1990 08 14 Appl. Data 145989 1988 01 20 Assignee Hitachi, Ltd. Hitachi Seibu Soft Ware Co., Ltd. Inventor(s) Chigira, Eiki Yokoyama, Takehiro State/Country JPX Title Method and apparatus for automatically generating program Abstract Automatic program generation method and apparatus in a computer program development support system having an input unit for inputting input information relating to data declaration and manner of use of data, a memory unit for storing a plurality of program part phototypes each including modifyable information and a processing unit for generating a program part from a program part prototype, wherein the input information is analyzed, one of the program part prototypes stored in the memory unit is selected in accordance with the analysis of the input information, and the selected program part prototype is substituted in accordance with the analysis of the input information to generate a program. U.S. Class 395/500 364/DIG1 364/261 364/286 IPC G06F 12/00 U.S. Refs 4546435 4604690 4712174 4730315 Priority JPX 19870123 62-13780 Patent Number 4949300 Issue Date 1990 08 14 Appl. Data 142587 1988 01 07 Assignee International Business Machines Corporation Inventor(s) Christenson, Patrick J. Martens, Craig W. Wenz, David G. Youngers, David N. State/Country MN Title Sharing word-processing functions among multiple processors Abstract A central processor holds a word-processing program and an entire document to be processed. A personal computer or intelligent terminal has an interactive display and holds code for some functions of the word processor, and stores individual pages of the document. As an operator performs editing tasks at the display, the personal computer performs locally those functions involving only the document page it holds. When additional document text is required to complete a function, the central processor performs the function on the full document. The central computer also performs all of certain other functions, regardless of where the data is stored. U.S. Class 395/145 364/DIG2 364/927.2 364/927.4 364/931.44 364/933.9 364/943 364/943.43 364/948.11 364/964 364/964.1 364/964.4 395/500 395/650 IPC G06F 15/16 G06F 15/21 U.S. Refs 4204206 4463442 4503499 4604710 4633430 Patent Number 4951195 Issue Date 1990 08 21 Appl. Data 151136 1988 02 01 Assignee International Business Machines Corporation Inventor(s) Fogg, Jr., Richard G. de Nicolas, Arturo M. State/Country TX Title Condition code graph analysis for simulating a CPU processor Abstract The system and method of this invention simulates the flow of control of an application program targeted for a specific instruction set of a specific processor by utilizing a simulator running on a second processing system having a second processor with a different instruction set. The simulator reduces the number of translated instructions needed to simulate the flow of control of the first processor instructions by performing a graph analysis on the application's instruction flow of control to determine which condition codes of each instruction are not needed for a subsequent instruction. Fewer translated instructions are needed if the condition codes for an instruction are not set or used subsequently. U.S. Class 395/500 364/DIG1 364/221.2 364/228 364/228.2 364/232.1 364/232.3 364/239.51 364/927.81 364/933.8 395/375 IPC G06F 9/00 U.S. Refs 3932843 4070705 4084235 4370709 4441154 4447876 4514803 4587612 4638423 4677587 4727480 4841476 Other Refs Graham, C., "Amiga's Trump Card: IBM PC Emulation", AmigaWorld, vol. 1, No. 2, Nov./Dec., 1985, pp. 34-35. "SoftPC", Insignia Solutions, Inc., ISI SoftPC Data Sheet Rev. 3.0, 1/87, 8 pages. Warner, E., "Unix-Based Workstations to Run DOS", Info World, 7/6/87, p. 8. May, C., "Mimic: A Fast System/370 Simulator"; SIGPLAN, 1987, Proceedings of the ACM SIGPLAN '87 Symposium on Interpreters and Interpretive Techniques, 6/87, 14 pages. Patent Number 4951245 Issue Date 1990 08 21 Appl. Data 196597 1988 05 20 Assignee Bull HN Information Systems Inc. Inventor(s) Bailey, Christopher R. M. Mandile, John R. Peters, Daniel G. Stonier, James W. State/Country NH Title Network terminal driver communications subsystem Abstract In a data processing system having a plurality of remote terminals, possibly of several kinds, connected by a plurality of communications media, also possibly of several kinds, from which terminals users may run a plurality of application programs in the central processing unit (CPU) of the data processing system, the CPU is provided with a network terminal driver for regulating transmissions between the various application programs and the various types of terminals over the various types of communications media. Means are provided for specifying the characteristics of the various types of application programs, terminals, and communications media, and the network terminal drive is responsive to those means. U.S. Class 395/275 364/DIG2 364/919 364/919.5 364/933.9 364/940 364/940.62 364/946.2 364/975.4 364/978.3 395/500 IPC G06F 3/00 G06F 13/38 U.S. Refs 3937925 4281315 4701841 4734853 4756007 4787028 Patent Number 4954942 Issue Date 1990 09 04 Appl. Data 272757 1988 11 17 Assignee Hitachi Ltd. Inventor(s) Masuda, Satoshi Kawasaki, Ikuya Matsui, Shigezumi State/Country JPX Title Software debugging system for writing a logical address conversion data into a trace memory of an emulator Abstract The microprocessor has an address converting buffer to convert logical addresses into physical addresses and a signal generator representing the timing for the microprocessor to retrieve conversion information from an external memory and write it into the address converting buffer. With this configuration, it is possible to determine the logical address from the physical address that was output to an external circuit, without the microprocessor outputting the logical address directly to the external circuit. U.S. Class 395/500 364/DIG1 364/231 364/231.31 364/232.3 364/232.8 364/238.4 364/239 364/239.9 364/240 364/244.7 364/249 364/249.2 364/254 364/254.3 364/255.1 364/255.2 364/255.8 364/256.3 364/256.4 364/256.5 364/256.6 364/258.1 364/259.6 364/259.9 364/260.4 364/264 364/264.5 364/267 364/267.91 364/270 364/280.4 395/575 IPC G06F 9/455 G06F 12/10 G06F 11/28 U.S. Refs 4218743 4574351 4636940 Other Refs "Virtual Address Trace Mechanism", Greer et al., IBM Technical Disclosure Bulletin, vol. 26, No. 2, Jul. 1983. "Nikkei Electronics", Nikkei McGraw-Hill, No. 414, Feb. 9, 1987, pp. 101-102. Priority JPX 19871120 62-293809 Patent Number 4956767 Issue Date 1990 09 11 Appl. Data 159179 1988 02 23 Assignee Stellar Computer, Inc. Inventor(s) Stephenson, R. Ashley State/Country MA Title Data processing system with model for status accumulating operation by simulating sequence of arithmetic steps performed by arithmetic processor Abstract A method accumulates the status of the execution of an arithmetic operation by an arithmetic processor having hardware elements for performing the steps of the operation, where each step is based on one or more operands and produces an intermediate or final result and possibly produces a corresponding status indicator. The method includes simulating the hardware elements in a model that performs simulated steps analogous to the steps performed by the hardware elements, each simulated step resulting in an intermediate or final status result; and while the arithmetic processor executes the arithmetic operation, applying each status indicator to the point in the model that corresponds to the point in the arithmetic processor where the result corresponding to the status indicator is applied, whereby the final result of the operation of the model will represent the accumulated status of the execution of the arithmetic operation. U.S. Class 395/500 364/DIG1 364/149 364/221.2 364/231.8 364/232.3 364/232.7 364/238.8 364/241.9 364/247 364/247.1 364/247.6 364/247.8 364/258 364/258.1 364/258.2 364/258.3 364/259 364/263 364/578 IPC G06F 7/46 G06F 9/455 G06F 15/36 G06F 15/46 U.S. Refs 3969722 4064394 4120043 4326263 4342093 4357678 4541071 4654812 4729105 4775950 4891773 Other Refs S. G. Tucker, "The IBM 3090 System: An Overview", IBM Systems Journal, vol. 25, No. 1, 1986, pp. 4-19. W. Buchholz, "The IBM System/370 Vector Architecture", IBM Systems Journal, vol. 25, No. 1, 1986, pp. 51-62. R. S. Clark et al., "Vector System Performance of the IBM 3090", IBM Systems Journal, vol. 25, No. 1, 1986, pp. 63-82. D. H. Gibson et al., "Engineering and Scientific Processing on the IBM 3090", IBM Systems Journal, vol. 25, No. 1, 1986, pp. 36-50. Y. Singh, "IBM 3090 Performance: A Balanced System Approach", IBM System Journal, vol. 25, No. 1, 1986, pp. 20-35. Patent Number 4958315 Issue Date 1990 09 18 Appl. Data 751350 1985 07 02 Assignee The United States of America as represented by the Secretary of the Navy Inventor(s) Balch, Kris S. State/Country CA Title Solid state electronic emulator of a multiple track motor driven rotating magnetic memory Abstract A system for emulating the memory characteristics of a motor-driven rotat memory having multiple heads per track and/or single heads per track with odd modular memory lengths. It is intended as a cost effective alternative for replacing magnetic rotating memories. The emulation is accomplished by multiplexing an offset memory address during each bit time. Non-volatile memory arrays translate the memory address to an offset address that is proportional to the odd modular track length of the multiple/single head track. Input/output registers are used for each read/write head that is emulated. An emulation address controller is used to generate all timing and initial addresses. U.S. Class 395/500 364/DIG2 364/927.81 364/952 364/952.2 364/952.9 364/960 364/961 364/961.4 IPC G06F 3/00 G06F 12/00 U.S. Refs Re31153 Re32075 3821715 3893088 3895360 4006457 4016547 4145745 4164041 4295205 4396959 4456971 Patent Number 4964039 Issue Date 1990 10 16 Appl. Data 243867 1988 09 13 Assignee Kabushiki Kaisha Toshiba Inventor(s) Izawa, Koji Takagi, Shiro Kamiyama, Tadanobu State/Country JPX Title Apparatus for processing code data associated with management data including identification data Abstract An information processing apparatus is provided with an optical disk for storing image data and code data. The code data stored in the optical disk have different data format. The optical disk further stores a flag indicating the data format of each code data. When retrieving the code data from optical disk, the processing apparatus processes the retrieved code data according to the data format indicated by the flag, and stores the processed data into a floppy disk. U.S. Class 395/500 364/DIG1 364/232.7 364/234 364/235 364/236.2 364/236.8 364/237.2 364/237.3 364/237.82 364/238.6 364/240 364/240.2 364/248.1 364/249.4 364/260.6 395/425 IPC G06F 1/00 U.S. Refs 4604653 4752929 Priority JPX 19870914 62-230027 Patent Number 4964074 Issue Date 1990 10 16 Appl. Data 306252 1989 02 02 Assignee Ando Electric Co., Ltd. Inventor(s) Suzuki, Noriyuki Asai, Hironobu State/Country JPX Title In-circuit emulator Abstract An in-circuit emulator comprising CPUs (microprocessors) of different types, portions of constituent elements thereof being different from each other, a control circuit connected to the CPUs and an external actual apparatus for controlling the operation of the in-circuit emulator, and an identifier circuit connected to the CPUs and the control circuit for identifying differences among the CPUs based upon feature signals from the CPUs inputted thereinto, the in-circuit emulator switching the control circuit to an operation mode suited to the CPU by making use of an output from the CPU identifier circuit. U.S. Class 395/500 364/DIG2 364/927.81 364/928 364/928.2 364/942.51 IPC G06F 9/455 G06F 13/00 U.S. Refs 4025906 4231087 4633417 4674089 Priority JPX 19860331 61-73648 Related Data This application is a continuation of U.S. Ser. No. 07/030 201, filed Mar. 24, 1987, now abandoned. Patent Number 4967346 Issue Date 1990 10 30 Appl. Data 167598 1988 03 14 Assignee Advanced Micro Devices, Inc. Inventor(s) Freidin, Philip State/Country CA Title Universal microprocessor interface circuit Abstract Interface circuitry (24) is provided which automatically detects which of two types of microprocessor is connected to the interface and configures the interface accordingly. A "type" flip-flop (36, 38) is initially set to expect a first type of microprocessor (10) and the interface is configured to expect a read and a write strobe. When a write cycle is performed by a second type (14) of microprocessor, the "type" flip-flop changes state and reconfigures the interface to expect a data strobe and a read/write indicator signal. U.S. Class 395/500 364/DIG1 364/232.8 364/239 364/239.9 364/240 364/240.5 IPC G06F 3/00 U.S. Refs 4287563 4379327 4641261 Patent Number 4972334 Issue Date 1990 11 20 Appl. Data 156169 1988 02 16 Assignee Hitachi, Ltd. Inventor(s) Yamabe, Michiru Konno, Chisato Umetani, Yukio State/Country JPX Title Automatic generation method of a simulation program for numerically solving a partial differential equation according to a boundary-fitted method Abstract A method is provided for automatically generating a simulation program which numerically solves a partial differential equation which governs a physical quantity in a non-rectangular real space domain. The real partial differential equation is solved according to a boundary-fitted method by first transforming the original partial differential equation from a real space to a normal space. The upper limit of user work area memory available on the data processing apparatus and the number of mesh points extracted from the real space domain shape are considered in the transformation and to an extent control the transformation rule. Two program statements are thus generated, the first of which allocates data area for the particular variables in the work area memory. The second program statement defines the value of each variable in terms of one factor. The final step combines the partial differential equation and the first and second program statements into a simulation program which is used to solve the original partial differential equation. U.S. Class 395/500 364/DIG1 364/191 364/224 364/232.3 364/260.4 364/260.9 364/261 364/578 IPC G06F 15/32 U.S. Refs 4580229 4636938 4730258 4736306 Other Refs Rice, J. R. et al., "Ellpack: Progress and Plans", Academic Press, 1981, pp. 135-162. "Twodepep a Problem-Solving System for Partial Differential Equations", IMSL Inc., 3rd ed., 1982. Umetani et al., "A Numerical Simulation Language for Vector/Parallel Processors", 1987, pp. 147-162. Morris, S. M., "SALEM-A Programming System for the Simulation of Systems Described by Partial Differential Equations", Fall Joint Computer Conference, 1968, vol. 33, pp. 353-358. Cardenas, A. F. et al., "A Language for Partial Differential Equations", Comm. ACM, vol. 13, No. 3, Mar. 1970. Priority JPX 19870313 62-56504 Patent Number 4975830 Issue Date 1990 12 04 Appl. Data 279846 1988 12 05 Assignee Dayna Communications, Inc. Inventor(s) Gerpheide, George E. Sharp, Kerry D. Lee, Daniel J. Olsen, David C. Meyer, David B. Kohagen, Mark E. State/Country UT Title Computer communication system having supplemental formats Abstract A computer communication system including a comunication medium, a plurality of nodes coupled to the communication medium, and a transfer format selection means for selecting a format for the transfer of data between nodes. The system includes at least one default node and at least two supplemented nodes. Each node has a set of data transfer formats. A default format is included in the format set of each node. Each supplemented node has at least one supplemental format. Transfer format selection means in the form of circuitry and software provides for the selection of a data transfer format which is included in the source node format set and the destination node format set and is compatible with the communication medium. The source node includes a cache of node format sets. The source node searches for the destination node format set in the source node cache and selects a format which is common to the format sets of the source node and destination node. Our invention also includes an attention signal, a network interface and the other devices, apparatus, methods and subject matter disclosed herein. U.S. Class 395/200 364/DIG1 364/222.2 364/228.3 364/229 364/229.1 364/235 364/240.8 364/242.95 364/260 364/284 364/284.3 364/284.4 395/500 395/575 IPC G06F 15/16 U.S. Refs 4777595 Patent Number 4975869 Issue Date 1990 12 04 Appl. Data 463835 1990 01 09 Assignee International Business Machines Corporation Inventor(s) Ammann, Lawrence M. Jackson, Howard C. Johnson, Charles D. Lutter, Edward P. State/Country VA Title Fast emulator using slow processor Abstract Software driven controller emulator includes hardware apparatus for emulating the controller at a speed faster than the software driven emulator, incorporating predicting a next event to be emulated and preactivating dedicated logic to emulate the controller driving the next event. In case of errors, the hardware controller sets a code signal and returns emulation to the software driven emulator for error recovery identified by the code signal. U.S. Class 395/575 364/DIG2 364/926.9 364/926.91 364/927.81 364/927.92 364/927.94 364/943.9 364/945 364/947 364/947.1 364/950 364/950.5 364/958.5 395/500 IPC G06F 9/455 U.S. Refs 4025902 4441154 4447876 4456954 4509122 4611277 4638423 4674089 4707803 4722047 4855905 Other Refs IBM System/360 and System/370 I/O Interface Channel to Control Unit Original Equipment Manufacturer's Information, Feb., 1988. Patent Number 4982361 Issue Date 1991 01 01 Appl. Data 789832 1985 10 21 Assignee Hitachi, Ltd. Inventor(s) Miyaoka, Shinichiro Muramatsu, Akira Funabashi, Motohisa State/Country JPX Title Multiple loop parallel pipelined logic simulation system Abstract The present invention is capable of registering and reading out a logical element for which the state of the output pin changes. The system includes an input side reading out circuit for reading out the kind of logical element and the states of all the input pins thereof, a decision circuit for deciding the presence of the output pin that the status change is produced on when a logical operation is carried out according to the kind of logical element, an output side reading out circuit for reading out the information related to the logical element of the output pin producing the status change, and an exchange sending circuit for sending each information read out from the output side reading out circuit to the desired registering and reading out circuit for precise high speed logic simulation of a large scale logic circuit containing MOS-type logical elements. U.S. Class 395/500 364/DIG2 364/221.2 364/231.8 364/232.3 364/263 364/264.3 364/916.3 364/931 364/931.4 364/933.8 IPC G06F 15/16 G06F 9/38 G06F 9/28 U.S. Refs 4070705 4087794 4229790 4247941 4306286 4308616 4342093 4351025 4365297 4396978 4466063 4584642 4587625 4590581 4604718 4635218 4644487 4656580 4656632 4751637 4763288 4783741 4785416 4788683 4873630 Other Refs 19th Design Automation Conference, 1982 IEEE, The Yorktown Simulation Engine: Introduction, Gregory F. Pfister, pp. 51-59. 20th Design Automation Conference, 1983 IEEE, HAL; A Block Level Hardware Logic Simulator, by Tohru Sasaki, et al., pp. 150-156. Gurd et al, "Data Driven System for High Speed Parallel Computing-Part 1: Structuring Software for Parallel Execution", Computer Design, Jun. 1980, pp. 91-100. Gurd et al, "Data Driven System for High Speed Parallel Computing-Part 2: Hardware Design", Computer Design, Jul. 1980, pp. 97-106. Kai Hwang, "Computer Architecture and Parallel Processing", McGraw-Hill, 1984, pp. 32-35, 374-375, 396-399, 448-449, 452-453, 762-763. R. Barto et al., A Computer Architecture for Digital Logic Simulation, Electronic Engineering (vol. 52, No. 642, Sep. 1980), pp. 35-36, 41, 45, 47, 50, 54, 56, 60, 63, 66. Priority JPX 19841026 59-223918 Patent Number 4985860 Issue Date 1991 01 15 Appl. Data 369358 1989 06 21 Inventor(s) Vlach, Martin State/Country OR Title Mixed-mode-simulator interface Abstract A mixed-mode-simulator interface synchronizes, at non-regular intervals, a system simulator which includes an analog realm and an event-driven realm, wherein both simulators perform a simulation on a single, mixed-mode system. The interface uses an error-driven procedure to time advance the analog realm, and uses events in the analog realm to time advance the event-driven realm. Polynomial interpolation rollback is used to adjust analog realm time location. U.S. Class 364/578 364/DIG1 364/DIG2 364/221.2 364/224 364/269 364/271 364/280.2 364/916 364/916.3 364/933.8 364/948 395/500 IPC G06J 1/00 U.S. Refs 3903402 4792913 Other Refs Arnout-IEEE Journal of Solid-State Circuits, vol. SC-13, No. 3, Jun. 1978, pp. 326-332. Fine-Electronic Engineering Times, Monday, Feb. 8, 1988. Corman-Electronic Engineering Times, Monday, Feb. 8, 1988. Sampson-VLSI Systems Design, Nov. 1988, pp. 70-78. Chadha-Proceedings of the IEEE International Conference on Computer-Aided Design, Nov. 7-10, 1988, pp. 258-261. Menzel-ISCAS, Feb. 1989, pp. 1145-1148. Patent Number 4989178 Issue Date 1991 01 29 Appl. Data 917054 1986 10 09 Assignee Omron Tateisi Electronics Co. Inventor(s) Shonaka, Hisashi State/Country JPX Title Programmable controller having forcibly set or reset I/O states controlled by stored flags in a flag memory Abstract A programmable controller includes an I/O memory for storing a plurality of input/output data items, a flag memory storing the same number of flags as the number of data items in the I/O memory, a data setter for writing set data or reset data into a relevant location in the I/O memory and for writing corresponding flag data into a relevant location of the flag memory in response to a certain I/O forced action operation, and a write control circuit for controlling the supply of writing pulses to the I/O memory by referring to the corresponding flag data of the flag memory for each item when writing data into the I/O memory during the execution of a command or during the updating of an input. U.S. Class 395/500 364/DIG2 364/916 364/916.3 364/926.9 364/927.2 364/927.4 364/928 364/933 364/933.2 364/933.8 364/946.2 364/949 364/964 364/969 364/969.1 364/969.2 364/975.2 IPC G06F 12/14 G06F 12/16 G06F 11/00 U.S. Refs 4122531 4298958 4388695 4439830 4441155 4442487 4528636 4554630 4574350 4592053 4602368 4651298 4651323 4672573 4703414 Priority JPX 19851011 60-226416 Patent Number 4992931 Issue Date 1991 02 12 Appl. Data 137674 1987 12 24 Assignee Kabushiki Kaisha Toshiba Inventor(s) Hirasawa, Yutaka State/Country JPX Title Data alignment correction apparatus for properly formatting data structures for different computer architectures Abstract An alignment correction apparatus includes: a first storage section for storing a source data stucture, a second storage section for sequentially storing input block data elements, an alignment data storage section, and a processor. The source data structure includes a plurality of data elements, and each block data element includes at least one data element. Alignment data includes a plurality of alignment data elements independently associated with the block data element. The processor sequentially reads out the alignment data elements from the alignment data storage section, in response to an alignment correction instruction. When the readout alignment data element is predetermined data, a block data element is read out from the first storage section and stored in the second storage section. When the readout alignment data element is not predetermined data, the next alignment data element is read out from the alignment data storage section. U.S. Class 395/500 364/DIG1 364/239 364/239.3 364/251 364/251.1 364/251.3 364/252.3 364/252.6 364/254 364/254.3 364/260.4 364/260.7 364/260.9 364/280 364/280.1 364/280.4 395/775 IPC G06F 3/00 G06F 9/45 U.S. Refs 3916388 3967101 4797810 4800520 4841435 Priority JPX 19861226 61-315330 Patent Number 4992934 Issue Date 1991 02 12 Appl. Data 504055 1990 03 30 Assignee United Technologies Corporation Inventor(s) Portanova, Gregory A. Sprague, Brian J. State/Country CT Title Reduced instruction set computing apparatus and methods Abstract A reduced instruction set computer (RISC) with a Harvard architecture is disclosed. The RISC may be designed to be used simply as a RISC or may be designed to be used to emulate a complex instruction set computer (CISC). Or, it may be designed for use as either. A CISC design methodology is disclosed whereby a RISC is designed and fabricated and whereby RISC emulation code is written concurrently with design and fabrication and also subsequent to fabrication. U.S. Class 395/375 364/DIG1 364/232.23 364/232.3 364/232.8 364/232.9 364/238 364/240 364/240.2 364/244.6 364/247 364/249 364/249.2 364/254 364/258.2 364/258.3 364/259.5 364/259.9 364/262.4 364/270 364/271 395/500 395/550 IPC G06F 9/40 U.S. Refs 4434462 4498135 4514801 4514805 4569016 4577282 4587612 4589065 4589087 4608634 4638426 4719568 4727480 Other Refs A VSLI RISC, by Patterson et al, IEEE Computer, Sep. 1982, pp. 8-18. The 801 Minicomputer, by Radin, IBM J. Res. Develop., vol. 27, No. 3, May 1983, pp. 237-246. Byington, L., Theis, D., "Air Force Standard 1750A ISA Is the New Trend", IEEE Computer, Nov. 1986, pp. 50-59. "Keeping an Eye on a Circuit Explosion", Electronic Design, Oct. 30, 1986. Tabak, D., "Which System Is a RISC?", IEEE Computer, Oct. 1986, pp. 85, 86. Fox, E. R., Kiefer, K. J., Vangen, R. F., Whalen, S. P., "Reduced Instruction Set Architecture for a GaAs Microprocessor System", IEEE Computer, Oct. 1986, pp. 71-81. Rasset, T. L., Niederland, R. A., Lane, J. H., Geideman, W. A., "A 31-bit RISC Implemented in Enhancement-Mode JFET GaAs", IEEE Computer, Oct., 1986, pp. 60-68. Meng, "Airborne Architecture Standard Holds On", Digital Design, Oct. 1986, pp. 24, 25. Silvey, A., Milutinovic, Mendoza-Grado, V., "A Survey of Advanced Microprocessors and HLL Computer Architectures", IEEE Computer, Aug. 1986, pp. 72-85. Colwell, R. P., Hitchcock, III, C. Y., Jensen, E. D., Sprunt, H. M. Brinkley, Kollar, C. P., "Computers, Complexity, and Controversy", IEEE Computer, Sep. 1985, pp. 8-19. Ohr, S., "RISC Machines", Electronic Design, Jan. 10, 1985, pp. 175-190. Patterson, D. A., "Reduced Instruction Set Computers", Communications of the ACM, Jan. 1985, vol. 28, No. 1, pp. 8-21. Hennesy, J. L., "VLSI Processor Architecture", IEEE Transactions on Computers, vol. C-33, No. 12, Dec. 1984, pp. 1221-1245. Ungar, D., Blau, R., Foley, P., Samples, D., Patterson, D., "Architecture of SOAR: Smalltalk on a RISC", 11th Annual Symposium on Computer Architecture, Jun. 4-7, 1984, Ann Arbor, Mich. Wulf, W. A., "Compilers and Computer Architecture", IEEE Computer, Jul. 1981, pp. 41-47. Related Data This is a continuation of application Ser. No. 06/941,450, filed Dec. 15, 1986, now abandoned. Patent Number 4992976 Issue Date 1991 02 12 Appl. Data 501306 1990 03 23 Assignee Fanuc Ltd Inventor(s) Yonekura, Mikio Kinoshita, Jiro State/Country JPX Title Method of allocating board slot numbers with altering software Abstract A method is provided of allocating board slot numbers in a control system composed of a plurality of boards which are subject to a variation in number and type. Slot numbers (12), in a maximum system (10) are determined to prepare software, and module identification numbers (13-18) of the boards at respective slots in a particular system (20) are read out. The read-out modules are converted to slot numbers (22) in the maximum system (10). Software in the maximum system can thus be executed without alteration. U.S. Class 395/500 364/DIG2 364/929.4 364/929.5 364/929.61 364/929.71 395/325 IPC G06F 13/14 G06F 12/10 U.S. Refs 4025903 4468729 4484273 4489414 4545010 4562535 4571676 4622633 4635192 4660141 4701878 Foreign Refs JPX 197912 54-16185 JPX 198212 57-20192 JPX 198312 58-22232 JPX 198408 59-14493 Priority JPX 19860418 61-89641 Related Data This is a continuation of copending application Ser No. 07/143,134 filed on Dec. 7, 1987 now abandoned. Patent Number 5003468 Issue Date 1991 03 26 Appl. Data 190648 1988 05 05 Assignee Hitachi, Ltd. Hitachi Computer Engineering Co. Inventor(s) Watanabe, Masaya Wakui, Fujio Abe, Shuichi State/Country JPX Title Guest machine execution control system for virutal machine system Abstract Mask data in a PSW are latched and sent from a host to a guest are subjected to a logical AND operation with latched data taken from an intervention request field of a state descriptor of the guest machine. The resultant logical product is used for setting the PSW of the guest machine and activating an interception to the host. The overhead of an execution controller managing the state transition between guest-host machines is reduced. U.S. Class 395/800 364/DIG1 395/375 395/500 IPC G06F 9/44 G06F 9/445 U.S. Refs 4400769 4456954 4779188 4816991 Priority JPX 19870511 62-114243 Patent Number 5003507 Issue Date 1991 03 26 Appl. Data 241385 1988 09 06 Inventor(s) Johnson, Simon State/Country WA Title EPROM emulator for selectively simulating a variety of different paging EPROMs in a test circuit Abstract An EPROM emulator makes use of a simple device with a housing connected to a eprom header which serves to connect the device to a circuit board in conjunction with a microprocessor emulator. Inside the housing are paging and data select circuits and a set of SRAM which are used in place of a traditional EPROM to hold the programming information. To program the device, the EPROM simulator is connected to the circuit board in place of an eprom. A switch on the housing is then turned to place the device in programming mode. The same switch also determines how the device is programmed by accessing the appropriate data lines for the number of pages of EPROM memory which are being emulated. After the switch is properly selected, the emulator is programmed by sending the data through the eprom socket on the circuit board via the microprocessor emulator. After the device is programmed, the switch on the housing is turned to place the device in read-only mode so that it can simulate an EPROM. In addition to the external switch, there are internal jumpers which are set to determine the type of EPROM which is to be emulated. U.S. Class 395/500 364/578 364/927.81 364/933.8 364/965 364/965.76 365/201 371/21.1 IPC G11C 7/00 G11C 29/00 U.S. Refs 4319341 4363109 4368515 4441167 4451903 4485457 4578751 4654829 4698790 4725983 Foreign Refs EPX 198603 0175102 Other Refs Ball, Stuart R., "Build The Emulo-8", Byte, Apr. 1986, pp. 105-110. Page Addressing Expands Addressable Memory in Up Systems, EDN, Apr. 30, 1987, pp. 189-197. Patent Number 5007017 Issue Date 1991 04 09 Appl. Data 035030 1987 04 06 Assignee Hitachi, Ltd. Inventor(s) Kobayashi, Hideaki State/Country JPX Title Method and apparatus for data communication through composite network Abstract Data communication through a composite network constituted by a plurality of mutually connected individual networks. When a center connected to a first network such as a wide-area telephone network and DDX for collecting information such as maintenance/management information performs data communication with a plurality of work stations connected to a network such as LAN, the information collecting center transmits a composite command containing collectively assembled addresses of the object work stations and operation commands to these stations. The composite command is disassembled in the second network. According to one method, the command is executed by the relevant work station upon reception of the composite command which is subsequently transferred to the succeeding station. U.S. Class 395/200 340/825.07 340/825.52 364/DIG2 364/918.7 364/919 364/919.4 364/927.92 364/927.96 364/931.4 364/933.9 364/940 364/940.1 364/940.61 364/940.62 364/940.63 364/940.71 364/940.92 364/942 364/942.08 364/946.2 395/500 IPC G06F 13/00 U.S. Refs Re30037 4016369 4034351 4039757 4058672 4058672 4195351 4374436 4379946 4413258 4471466 4477882 4510492 4596013 4627052 4680581 4706080 4706081 Other Refs "Overview, How IBM addresses LAN requirements with the token ring," Data Communications, pp. 120-124, Feb. 1986. Priority JPX 19860404 61-77841 Patent Number 5021948 Issue Date 1991 06 04 Appl. Data 031280 1987 03 30 Assignee Kabushiki Kaisha Toshiba Inventor(s) Nakayama, Yasuko Aida, Kazuo State/Country JPX Title Program counter display device Abstract A program counter display device having a program memory which stores a source program. An interpreter reads out the source program from the program memory and executing it. A program list generator generates a program list of the program stored in the program memory, and a program flow monitor having knowledge of the program flow determines the program flow in accordance with the statement currently being executed. A control structure monitor correlates the current statement supplied from the interpreter with a program control structure, and checks the balance of the program control structure such as the existence of an end in a loop structure, the existence of a destination of a branch sentence, etc. A program counter-mark generator connected to the program flow monitor and the control structure monitor generates a program counter mark indicating the program counter function, the program flow, and the control sturcture. A display device connects to the program list generator and to the program counter mark generator and displays the program counter mark in association with the program list. The program counter mark is constituted by a box section which is displayed over the range of the program list included in the program control structure. A direction-indicating section is displayed within the box section, and indicates which statement is currently being executed, and also the direction of program flow. When the arrow of the direction-indicating section is pointing right, the arrow is pointing to the current statement; when the arrow is pointing upward or downward, the arrow is indicating the program flow. U.S. Class 395/500 364/DIG1 364/234.3 364/237.2 364/237.5 364/243.3 364/247 364/247.2 364/247.7 364/254 364/254.6 364/255.2 364/264.3 364/265.6 364/267 364/267.4 364/267.8 364/267.91 364/280 364/280.4 364/286 371/19 395/275 IPC G06F 9/455 U.S. Refs 3522597 3987420 4009379 4181965 4275441 4376977 4445169 4571677 4636940 4730315 4872167 Other Refs Ralston, A. and E. D. Reilly, Jr., "Software Erros," Encyclopedia of Computer Science and Engineering, p. 616 (2nd Ed. 1983). Mare H. Brown and Robert Sedgewick, "A System for Algorithm Animation", Computer Graphics, vol. 18, No. 3, Jul. 1984, pp. 177-186. Marc H. Brown and Robert Sedgewick, "Techniques for Algorithm Animation," IEEE Software, vol. 2, No. 2, Jan. 1985, pp. 28-29. James E. Brink and Richard J. Spillman, Computer Architecture and VAX Assembly Language Programming, The Benjamin/Cummings Publishing Company, Inc., Menlo Park, California, 1987, pp. 536-555. Marc H. Brown and Robert Sedgewick, "Progress Report: Brown University Instructional Computing Laboratory," ACM SIECSE Bulletin, vol. 16, No. 1, Feb. 1984, pp. 91-101. Marc H. Brown, Norman Meyrowitz, and Andries van Dam, "Personal Computer Networks and Graphical Animation: Rationale and Practice for Education," ACM SIECSE Bulletin, vol. 15, No. 1, Feb. 1983, pp. 296-307. A Tutorial Introduction to ADB; Maranzano et al.; May 5, 1977. Microsoft Code View; Microsoft Corporation; 1986. Priority JPX 19860329 61-72162 Patent Number 5023778 Issue Date 1991 06 11 Appl. Data 498080 1990 03 23 Assignee General Motors Corporation Delco Electronics Corp. Inventor(s) Simon, Jr., Robert C. Deutscher, Dale W. Grimm, Charles M. Thompson, Dennis D. Bailey, Kirk A. State/Country MI Title Interprocessor communication method Abstract A communication method provides for an exchange of a multiple byte message between two processors. Interrupt suppression associated with the message transfer is minimized by alternating the processors between master and slave operating modes with each byte exchanged. U.S. Class 395/325 364/DIG1 364/222.2 364/228 364/230 364/230.2 364/230.3 364/230.4 364/238.7 364/239.9 364/244 364/244.5 364/247 364/247.4 364/260 364/284 364/284.3 395/500 IPC G06F 15/16 G06F 13/00 U.S. Refs 4047159 4418382 4473879 4511968 4577273 4590554 4654784 4669044 4866597 4870571 4882727 Other Refs Motorola Semiconductor Technical Data, MC68HC11A8 HCMOS Single-Chip Microcomputer Advance Information, pp. 1.varies.6 through 6-6, 1985. Patent Number 5025364 Issue Date 1991 06 18 Appl. Data 067987 1987 06 29 Assignee Hewlett-Packard Company Inventor(s) Zellmer, Joel A. State/Country CO Title Microprocessor emulation system with memory mapping using variable definition and addressing of memory space Abstract A memory mapper for an emulation system suitable for a microprocessor-based system for any size microprocessor is disclosed which uses function code comparators, range comparators, and offset values for individual mapping definitions, thereby providing faster mapping of emulation memory with higher resolution and flexibility in making changes. A single mapper cell is used for implementing each separate mapping definition. The function code comparator for the mapper cell defines the type of memory, the range comparator defines the section of memory covered by the mapper definition, and a translator is used to translate the original address to a translated address by adding an offset to the original address. Original addresses which do not match any mapper cell definitions are mapped according to a default definition. U.S. Class 395/500 364/DIG1 364/232.3 364/232.8 364/238.4 364/246.3 364/252.5 364/255.2 364/259.1 364/259.2 364/259.7 364/927.81 364/927.97 364/947.1 364/947.2 364/947.4 364/955.3 364/958.2 364/966.4 IPC G06F 9/355 G06F 9/455 G06F 12/02 G06F 7/02 U.S. Refs 4104718 4155199 4325120 4354225 4453211 4514803 4514805 4516199 4527237 4674089 4720778 4796258 Patent Number 5036457 Issue Date 1991 07 30 Appl. Data 185888 1988 04 22 Assignee Nucleus International Corporation Inventor(s) Glaser, Edward L. DesJardins, Paul R. Caldwell, Douglas W. Glaser, Eliot D. State/Country CA Title Bit string compressor with boolean operation processing capability Abstract An apparatus and method, for use with a computer, for converting an uncompressed one-dimensional array of binary bits into a compressed binary bit string and/or for processing a Boolean operation on a first and a second compressed bit string. The first and second bit strings each contain one or more impulses. An impulse contains a run, which is a string of one or more bits of the same binary value, and an ending bit having a polarity opposite the polarity of the run. The impulses are encoded in one or more compressed impulse formats. Each compressed impulse format contains at least a first and a second indicator. The first indicator is for indicating the binary value of one or more same polarity bits of the run and the second indicator is for indicating the length of bits of the impulse. The length of bits is a quantity of the same polarity bits of the run and/or the ending bit having a polarity opposite the run. U.S. Class 395/500 341/50 341/51 341/63 341/64 364/DIG1 364/236.3 364/236.4 364/248.2 364/259 364/259.1 364/259.2 364/259.8 364/259.9 364/260.1 364/260.4 364/260.6 364/268.3 364/268.8 364/282.1 395/650 IPC H03M 7/00 U.S. Refs 2853698 3400380 3717851 4117470 4319225 4464650 4558302 4586027 4626829 4706265 Other Refs "Run-Length Encodings"-Solomon W. Golomb, Department of Electrical Engineering, University of Southern California, Los Angeles, Calif., (1966). "Optimizing a Scheme for Run Length Encoding"-Stevan D. Bradley, (Published Proceedings of the IEEE, Jan., 1969). "Encoding Verbal Information as Unique Numbers"-W. D. Hagamen et al., (Published IBM Syst. J., No. 4, 1972, pp. 278-315). Related Data This application is a continuation-in-part application of the patent application which is the subject of Ser. No. 07/100,761, filed oh Sept. 24, 1987, now abandoned the priority of which is claimed and the entire disclosure of which is incorporated by reference. The subject matter of this application is related to copending application entitled A RELATIONAL DATABASE REPRESENTATION WITH RELATIONAL DATABASE OPERATION CAPABILITY to Glaser, et. al., Ser. No. 07/107,447, filed on Oct. 9, 1987 now abandoned in favor of continuation-in-part application Ser. No. 07/238,754, filed Aug. 29, 1988. Patent Number 5036484 Issue Date 1991 07 30 Appl. Data 275341 1988 11 23 Assignee International Business Machines Corporation Inventor(s) McCoy, Glenn C. Yiskis, Eric N. State/Country NY Title Personal computer/host emulation system for handling host data with personal computer application programs at personal computers Abstract A system for emulating the operation of a terminal connected to a host computing system while retaining the ability to utilize personal computer application programs resident in the personal computer by utilizing a personal computer/host terminal emulation program which conducts an analysis of host data and keystrokes to identify personal computer commands and calls the appropriate resident application program in response to such commands. U.S. Class 395/500 364/DIG2 364/927.81 364/927.82 364/927.98 364/928 364/928.3 364/928.6 364/933.9 364/943.44 364/948.1 364/948.3 364/948.9 364/962.1 364/975.1 364/976.1 364/977 IPC G06F 15/16 G06F 15/18 U.S. Refs 3955180 4291372 4482955 4513373 4611277 4791561 4896290 4896291 4899136 4903218 Patent Number 5038279 Issue Date 1991 08 06 Appl. Data 529695 1990 05 22 Assignee Lexmark International, Inc. Inventor(s) Bertram, Randel L. Hays, Douglas E. Lederer, James F. State/Country KY Title Direct hot-keying with reset of printer parameters for a secondary application including a typewriter emulator Abstract A computer system operating under software control to provide output to a printer for printing. The computer system sets printer parameters to accommodate different forms of output to the printer. A word processing program stored in the computer memory is executed to couple information for printing to the printer with the printer in a first set of printer states. A typewriter emulator program stored in the computer memory is executable to couple information for printing to the printer and to set the printer states. The word processing program is interrupted by a hot key depressed by an operator, and the typewriter emulator program is entered, with the printer states being set in dependence upon printer state information for the typewriter emulator. When the typewriter emulator is interrupted by a hot key, the then-current printer states are stored and a set of default printer states for the word processor are restored prior to returning to execution of the word processing software. U.S. Class 395/500 364/DIG1 364/225 364/225.6 364/232.3 364/235 364/236 364/239.3 364/242.1 364/260.4 364/274.1 364/275.1 364/280.7 395/725 IPC G06F 3/02 G06F 3/03 G06F 7/00 U.S. Refs 4106101 4195353 4212077 4284362 4377852 4458311 4458331 4539653 4603385 4641263 4642792 4709349 4716543 4727480 4750116 4775953 Patent Number 5045994 Issue Date 1991 09 03 Appl. Data 910668 1986 09 23 Assignee Bell Communications Research, Inc. Inventor(s) Belfer, Daniel F. Lech, Ann G. Perelmuter, Isaac M. Ward, Jerry J. State/Country NJ Title Emulation process having several displayed input formats and output formats and windows for creating and testing computer systems Abstract A method of operating a computer system is disclosed that facilitates the creation and testing of application system software by utilizing an autonomous environment to emulate the application system environment. The emulation environment allows the user to call into view sequences of standard input-output (I/O) screen format pairs normally used to submit information to and receive information from the application system. In the emulation mode, these screens are prepared off-line and stored until the user desires to exercise the application system. Each input format is filled with information that will serve as actual input to the application system when it is exercised. Each output format is filled with information that comprises expected results when the application system is actually exercised. The expected results are compared to actual results after execution of each I/O pair and further application system processing is controlled by the comparison results. The stand-alone emulation environment provides editing and control routines and library functions to aid the user in defining and modifying the I/O sequences. U.S. Class 395/500 364/DIG1 364/232.3 364/237.2 364/237.3 364/264 364/264.3 364/264.5 364/286 364/286.1 364/286.2 395/425 IPC G06F 9/455 G06F 3/14 U.S. Refs 4458331 4509122 4570217 4601010 4604710 4727480 Other Refs "The LEAP Load and Test Driver", Dolotta, Licwinko, Menninger and Roome, IEEE Catalog No. 76CH1125-4C, pp. 182-186. Patent Number 5050069 Issue Date 1991 09 17 Appl. Data 042761 1987 04 27 Assignee Thinking Machines Corporation Inventor(s) Hillis, W. Daniel Kahle, Brewster Robertson, George G. Steele, Jr., Guy L. State/Country MA Title Method and apparatus for simulating m-dimension connection networks in and n-dimension network where m is less than n Abstract In accordance with the invention, each element or mode in the n-dimensional connection pattern is assigned a unique binary number or address by numbering the elements. Next, the individual binary digits of the address associated with each element are assigned to the different dimensions of the connection pattern of m dimension according to a fixed rule. Each set of binary digits that is so assigned to a dimension is then treated as the address of the node in that dimension in a gray code space; and the nodes that are its nearest neighbors in that dimension are those nodes that bear the Gray code values immediately before it and immediately after it in the Gray code sequence. Data are then routed to the nearest neighbor in one direction in a dimension by forwarding them from one node to the node bearing the next succeeding (or preceding) Gray code address and a node can be conditioned to receive such data by having it look for data from the node with the next preceding (or succeeding) address. U.S. Class 395/500 364/DIG1 364/229 364/229.4 364/231.9 364/238.1 364/238.2 364/238.3 364/259.1 364/264.3 364/284 364/284.4 IPC G06F 13/20 U.S. Refs 4065808 4523273 4598400 4639857 4644496 4709327 4727474 4739476 Foreign Refs JPX 198501 6015768 Other Refs E. N. Gilbert, "Gray Codes and Paths on the N-Cube.", The Bell System Technical Journal (May 1958), pp. 815-826. Martin Gardner, "The Binary Gray Code." In: Knotted Doughnuts and Other Mathematical Entertainments, W. H. Freeman and Company, New York, (pp. 11-27). W. Lin et al., "Reconfiguration Procedures for a Polymorphic and Partitionable Multiprocessor.", IEEE Transactions on Computers, vol. C-35, No. 10, (Oct. 1986), pp. 910-915. T. Bartee, "Read-Only Memories", in: T. Bartee Digital Computer Fundamentals (New York, McGraw-Hill Book Company, 1977), pp. 316-318. H. Taub et al., "The Grey Reflected Binary Code", in: H. Taub et al., Digital Integrated Electronics (New York, McGraw-Hill, Inc., 1977), pp. 106-107. F. P. Preparata et al., "The Cube-Connected Cycles: A Versatile Network Parallel Computation", Communications of the ACM, vol. 24, No. 5, (May 1981), pp. 300-309. NCR Handbook (NCR45CG72), "Geometric Arithmetic Parallel Processor", 1st Ed., Dayton, Ohio, NCR Corporation, 1984, pp. 1-12. NCR Handbook (NCR45CG72 GAPP Application Note No. 3), "Detection of Edges and Gradients in Binary and Gray Scale Images with the Gapp Processor", 1st ed., Dayton, Ohio, NCR Corporation, 1985, pp. 1-23. L. Adams, "Modeling Algorithm Execution Lime on Processor Arrays.", IEEE Computer (Jul. 1984), pp. 38-43. R. Asbury et al., "Concurrent Computers for Inherently Parallel Problems", Computer Design (Sep. 1, 1985), pp. 99-102, 104, 106, 107. K. Batcher, "Design of a Massively Parallel Processor", IEEE Transactions on Computers, vol. C-29, No. 9 (Sep. 1980), pp. 836-840. T. Hoshino t al., "An Invitation to the World of PAX", IEEE, Computer (May 1986), pp. 68-79. C. Seitz, "The Cosmic Cube", Communications of the ACM, vol. 28, No. 1, (Jan. 1985), pp. 22-33. Patent Number 5051888 Issue Date 1991 09 24 Appl. Data 292590 1988 12 30 Assignee Hewlett Packard Company Inventor(s) Hansen, John D. Berger, Arnold S. Kootstra, Lewis S. Jones, Beth V. Bowlin, Stan W. Fleck, William State/Country CO Title Data processing systems for coordinating measurement activity upon a plurality of emulators Abstract A system for coordinating the measurement activity of a plurality of emulators and their associated internal analyzers uses a bus with three signal lines. A READY signal is set false by any emulator that initiates a break (a transition from running user code to running a monitor). The READY signal is set false by the breaking emulator at the very beginning of its break, without waiting for the resumption of the monitor program. The false ready signal is detected immediately by the other emulators, which then break in sympathy. The READY signal is further used to restart all emulators in unsion. The emulator that initiated the break remains running its monitor, while the others start their monitors, determine that they did not cause the break, and then in anticipation of a restart, essentially suspend their monitors and prepare to start running user code. As each emulator becomes ready it releases the READY signal. As the last emulator becomes ready, it too releases READY, which then goes true. At this all emulators complete their escape from their monitors (which for each of them amounts to just an instruction fetch, or so) and resume execution of their user code. A four-state state machine in each emulator assists in this, and is in part, advanced through its states by transitions in the READY signal. The four states correspond to: running the monitor, ready to start executing user code, executing user code, and invoking the monitor. A TRIGGER signal is available to allow analyzers to trigger other analyzers, or to cause an emulator to break. An EXECUTE signal is available to allow a single command issued to any emulator to cause target system starts from preselected initial conditions. U.S. Class 395/500 364/DIG1 364/229 364/230 364/232.3 364/260 364/264 364/264.1 364/267 IPC G06F 9/06 G06F 15/16 G06F 9/455 G06F 13/12 U.S. Refs 4180854 4782461 4961162 Foreign Refs JPX 198509 60-83144 JPX 198509 60-86632 JPX 198811 63-167939 Patent Number 5051938 Issue Date 1991 09 24 Appl. Data 370896 1989 06 23 Inventor(s) Hyduke, Stanley M. State/Country CA Title Simulation of selected logic circuit designs Abstract A system and method for selectively simulating logic circuit designs in which a data tables generator receives information from a schematic entry program or netlist entry file and produces data tables for use by a simulator. A designer provides inputs to the data tables generator from a schematic entry program or a netlist entry file. The data tables generator generates from the information received a table of used integrated circuits and a table of their connections. A simulator then receives the output from the data tables generator and produces a design simulation program table that executes integrated circuit model subroutine stored in an integrated circuit model reference library and netlist subroutines stored in a netlist connectivity table. The system may also be used for testing logic circuits on a printed circuit board by capturing signals from a potentially defective logic section of the printed circuit board and feeding them into test points of the integrated circuit simulated by the computer simulator. U.S. Class 364/578 364/DIG2 364/488 364/580 364/916 364/916.2 364/916.3 364/916.4 364/921.8 364/921.9 364/927.8 364/929.4 364/929.5 364/929.71 364/930 364/931.01 364/933.9 364/948.2 364/955 364/955.5 364/966.2 364/978.2 371/23 395/275 395/500 IPC G06G 7/48 G06F 11/00 U.S. Refs 3961250 4587625 4744084 4782440 4791593 4802165 4817093 4827427 4882690 4891773 4896272 4939681 4967386 Other Refs Darringer, J. A., "A New Look at Logic Synthesis", 17th D.A. Conference 1980, pp. 543-549. Nash et al., "A Front End Graphic Interface to the First Silicon Complier" European Conference on Electronic Design Automation, 26-30 Mar. 1984, pp. 120-125. de Geus et al., "A Rule-Based System for Optimizing Combinational Logic", IEEE Design and Test, Aug. 1985, pp. 22-32. Patent Number 5051941 Issue Date 1991 09 24 Appl. Data 478511 1990 02 12 Assignee Hitachi, Ltd. Inventor(s) Takamine, Yoshio Miyamoto, Shunsuke Nakagawa, Takayuki Kazama, Yoshiharu Kinoshita, Yoshiaki State/Country JPX Title Method and apparatus for logical simulation Abstract A method of logic simulation for simulating operation of a logic circuit by using basic signal values corresponding to states of output signals of elements of the logic circuit to be simulated and expanded signal values including the basic signal values. The logic circuit to be simulated is divided into a portion to be simulated by using the basic signal values and the expanded signal values and a portion to be simulated by using the basic signal values without using the expanded signal values. The elements for which definition of calculation method for output signal values for the input signal values including the expanded signal values is not easy are included in the latter portion, and other elements are included in the former portion. A virtual signal conversion element for converting the expanded signal into the basic signal is provided at a position where a signal is sent from the former portion to the latter portion so that the expanded signal value outputted from the element of the former portion is converted into the basic signal value before it is sent to the element of the latter portion. U.S. Class 364/578 364/DIG1 364/221 364/221.2 364/260.4 364/264.3 395/500 IPC G06F 15/20 G06F 9/44 U.S. Refs 4342093 4587625 4635218 4694411 4725971 Priority JPX 19860926 61-225937 Related Data This is a continuation of application Ser. No. 101,023, filed Sept. 25, 1987 and now abandoned. Patent Number 5056013 Issue Date 1991 10 08 Appl. Data 435959 1989 11 14 Assignee NEC Corporation Inventor(s) Yamamoto, Mitsuhiro State/Country JPX Title In-circuit emulator Abstract An in-circuit emulator comprising an emulation microprocessor for directly outputting at least an address and an execution level information, a latch circuit for latching at least the execution level information outputted from the emulation microprocessor, a register holding a execution level information to be traced, a comparator receiving respective contents of the latch circuit and the register for generating an enable signal when the execution level information latched in the latch circuit is consistent with the execution level information to be traced of the register, and a trace memory coupled to receive the address outputted from the emulation microprocessor and responding to the enable signal so as to store the address outputted from the emulation microprocessor, whereby only the result of execution belonging to a selected execution level is traced in the trace memory. U.S. Class 395/500 364/230 364/230.4 364/232.3 364/240 364/241.9 364/246.6 364/246.9 364/247 364/247.6 364/247.8 364/259 364/259.2 364/259.9 364/260 364/267.91 364/271 364/271.4 364/280 371/16.2 371/19 IPC G06F 11/00 U.S. Refs 4205370 4453093 4571677 4598364 4636940 4674089 4802165 4847805 4879646 4933941 Foreign Refs EPX 198308 0085437 JPX 198405 59-77553 JPX 198411 59-205652 JPX 198505 60-84643 JPX 198512 60-262251 JPX 198706 62-137626 JPX 198707 62-168243 JPX 198712 62-286134 JPX 198805 63-123140 JPX 198811 63-271553 Priority JPX 19881114 63-288585 Patent Number 5056015 Issue Date 1991 10 08 Appl. Data 326811 1989 03 21 Assignee Du Pont Pixel Systems Limited Inventor(s) Baldwin, David R. Wilson, Malcolm E. Trevett, Neil F. State/Country GBX Title Architectures for serial or parallel loading of writable control store Abstract A multiprocessor subsystem, wherein each processor is separately microcoded so that the processors can run concurrently and asynchronously. To conserve lines and provide flexibility in specifying the subsystem configuration, a serial loop interface preferably provides the data access from the higher-level processor to all of the control stores. To maximize the net bandwidth of this loop, each separate control store preferably interfaces to this serial line using a bank of serial/parallel registers which can load the instructions into the control store, or clock the instruction stream incrementally, or simply clock the instruction stream along as fast as possible. Thus, the bandwidth of this line is used efficiently, and only a minimal number of instructions is required to access control storage for a given processor. One of the processors is a numeric processing module, which is connected to a cache memory by a very wide cache bus. This processor can receive programs either over the serial loop or over the cache bus. The use of the wide cache bus for parallel microinstruction transfer permits fast microcode overlaying. This system even makes dynamic paging of microcode practical in some applications. U.S. Class 395/500 364/DIG1 364/228.6 364/230 364/230.1 364/230.5 364/239 364/239.2 364/242.3 364/242.31 364/243 364/243.41 364/244 364/244.5 364/244.6 364/247 364/247.4 364/247.8 364/260 364/262.4 364/262.7 364/262.8 395/275 395/425 395/725 IPC G06F 12/00 U.S. Refs 3623017 4030072 4149242 4161024 4172287 4208716 4245307 4323968 4463421 4484270 4722049 Foreign Refs EPX 198602 0186150 EPX 198610 0085435 WOX 198604 WO86/07174 GBX 198601 2162406a Other Refs Proceedings of the IEEE, vol. 73, No. 5, May 1985, pp. 852-873, IEEE, New York; J. Allen: "Computer Architecture for Digital Signal Processing". Computer Design, vol. 16, No. 6, Jun. 1977, pp. 151-163; A. J. Weissberger: "Analysis of Multiple-Microprocessor System Architectures", FIGS. 7, 8, p. 161. IEEE Electro, vol. 8, Apr. 1983, pp. 3/3 1-5, New York; B. J. New: "Address Generation in Signal/Array Processors". Proceedings ICASSP, Dallas, 6th-9th Apr. 1987, vol. 1, pp. 531-534; D. M. Taylor et al.: "A Novel VLSI Digital Signal Processor Architecture for High-Speed Vector and Transform Operations". IBM Technical Disclosure Bulletin, vol. 27, No. 4A, Sept. 1984, pp. 2184-2186, New York; J. P. Beraud et al., "Fast Fourier Transform Calculating Circuit". Bureaux D'Etudes Automatishmes, No. 32, Mars 1987, pp. 85-87; J. Gustafson: Un Super-Ordinateur Vectoriel Homogene, p. 85, figure; p. 85, left-hand col., line 35--p. 87, middle col., line 9. Conference Proceedings IEEE Southeastcon '87, Tampa, Fla., Apr. 1987, vol. 1, pp. 225-228; M. C. Ertem: A Reconfigurable Co-Processor for Microprocessor Systems, Figs. 2-4; p. 226, left-hand col., line 6--p. 227, left-hand col., line 25. Proceedings of the Fourth Euromicro Symposium on Microprocessing and Microprogramming, Munich, Oct. 1978, pp. 358-365; F. B. Jorgensen et al.: A Bi-Microprocessor Implementation of a Variable Topology Multiprocessor Node, Figs. 1-6, pp. 358, right-hand col., line 13--p. 362, right-hand col., line 21. G. J. Myers: Digital System Design with LSI Bit-Slice Logic, 1980, pp. 230-239, John Wiley & Sons, Inc., U.S., p. 237, lines 1-4. Priority GBX 19880323 8806855 GBX 19880323 8806869 Patent Number 5058001 Issue Date 1991 10 15 Appl. Data 407678 1989 09 14 Assignee International Business Machines Corporation Inventor(s) Li, Hungwen State/Country NY Title Two-dimensional array of processing elements for emulating a multi-dimensional network Abstract Two-dimensional mesh architecture in an array processor of myriad processing elements allows relative ease in manufacturing, using planar integrated circuits and predominant X, Y connections. There is a need, in any array processor, to connect a selected processing element to another processing element. Rather than to supply the large number of connectors required for dedicated connection of processing element to processing element, implementation is by a very limited number of connecting conductors (NESW) in a two-dimensional mesh. The connecting conductors are coplanar, making construction compatible with present-day, essentially planar and predominantly XY, packaging of integrated circuits and printed circuit boards. Flexibility of interconnection by means of this limited and inflexible set of conductors is accomplished by equipping each processing element with a hopping circuit. This is an advantageous tradeoff of silicon area, since the few active elements of the hopping circuit consume much less silicon area than the large number of conductors otherwise required. The hopping circuits are programmable, by a shared routing controller, to send input to an internal register file within the processing element, or to respond to a HOP (direction)(step) command. The HOP command selects the direction parameter by selecting one of the limited external connections to an adjacent processing element. Connection to a remote processing element requires a number of HOP command steps, carried out in a series of cycles. Each hopping circuit includes multiplexer, sink register, demultiplexer and gates. U.S. Class 395/500 364/DIG1 364/229 364/229.5 364/231.9 364/232.8 364/260.1 364/260.4 364/262 364/736 IPC G06E 15/80 U.S. Refs 4174514 4215401 4247892 4309691 4314349 4380046 4398176 4514807 4523273 4601055 4633431 4639857 4709327 4718005 4739474 4739476 4910665 Other Refs "Geometric Arithmetic Parallel Processor", NCR, 1984, pp. 1-12. "The Connection Machine", W. Daniel Hillis, The MIT Press, pp. 21, 71-80. "Clip 4 Parallel Processing System", Fountain et al, IEEE Proc., vol. 127, Pt. E, No. 5, Sep. 1980, pp. 219-224. "Design of a Massively Parallel Processor", Kenneth Batcher, IEEE Transaction of Computer, vol. C-29, No. 9, Sep. 1980, pp. 836-840. M. V. A. Hancu et al, "A Systolic Scheme for Fast Parallel Communication in VLSI Mesh-Connected Parallel Computers". Related Data This application is a continuation of application Ser. No. 07/022,194 filed Mar. 5, 1987, now abandoned. Patent Number 5062034 Issue Date 1991 10 29 Appl. Data 440455 1989 11 20 Assignee U.S. Philips Corporation Inventor(s) Bakker, Jacobus M. State/Country NLX Title Device for emulating a microcontroller using a parent bond-out microcontroller and a derivative non-bond-out microcontroller Abstract The device includes a parent microcontroller in a bond-out version and a derivative microcontroller in a non-bond-out version, in order to emulate the derivative microcontroller. To this end, the parent microcontroller is connected to an external program memory by means of memory connection pins. The derivative microcontroller comprises an additional functional processing facility, an internal program memory and a processor element. Upon emulation the derivative microcontroller receives an emulation control signal. Communication means between the processor and the internal program memory on the one side and the additional functional process facility on the other side are thus deactivated. Finally, the two microcontrollers are interconnected and connected to an external program memory in such a manner that a series of standard pins and the processor of the parent microcontroller are activated, and the external processing section of the derivative microcontroller and said external program memory are activated. U.S. Class 395/500 364/232.3 364/232.8 364/232.9 364/237.2 364/237.4 364/238.4 364/238.6 364/238.9 364/240 364/241.9 364/243 364/243.3 364/244 364/244.6 364/247 364/247.1 364/247.6 364/247.8 364/251 364/251.3 364/259 364/259.9 364/261.3 364/261.5 364/262.4 364/264 364/267 364/267.4 364/267.6 IPC G06F 11/30 U.S. Refs 108832 4370709 4514805 4527234 4591975 4607366 4633417 4674089 4689740 4720778 4739475 4764926 4785416 4809167 4811345 4847805 4868822 Foreign Refs DDX 198609 0238713 JPX 198209 0143650 Other Refs Moon, Jim, "Microcomputer for Emulation Bares Hidden Buses, Functions", Electronics, Jul. 17, 1980, pp. 126-129. Williams, Mike, "A Modular Approach to Microcontroller Emulation", Electronic Engineering, Oct., 1988, pp. 59-66. "Single-Chip 8-Bit Microcontrollers, USER Manual", Philips Electronics Components & Materials Division, Eindhoven, The Netherlands, 1986, pp. 323-332. Priority NLX 19861111 8602849 Related Data This is a continuation of application Ser. No. 116,603, filed Nov. 2, 1987 now abandoned. Patent Number 5063499 Issue Date 1991 11 05 Appl. Data 294831 1989 01 09 Assignee Connectix, Inc. Inventor(s) Garber, Jonathan F. State/Country CA Title Method for a correlating virtual memory systems by redirecting access for used stock instead of supervisor stock during normal supervisor mode processing Abstract A method for causing suitably configured versions of the Apple Macintosh computer running the Apple Macintosh operating system to operate in user mode while causing at least user programs to continue to perform as though operating in supervisor mode, and in conjunction therewith a further method for implementing virtual memory on such Apple Macintosh computer systems. U.S. Class 395/500 364/DIG1 364/231 364/232.3 364/232.9 364/236.2 364/236.3 364/244 364/244.3 364/246 364/246.11 364/246.3 364/246.6 364/246.8 364/248.1 364/248.2 364/254.8 364/256.3 364/256.6 364/261 364/262.4 364/262.9 364/280 364/280.2 IPC G06F 12/02 U.S. Refs 3815103 4493035 4519032 4528624 4542458 4592011 4617624 4669043 4714993 4825358 4849878 4868738 Other Refs "Editorial--'89 Won't be Apple's Year of Multitasking", MacWeek, Jan. 3, 1989 p. 22. "Virtual Memory Ends RAM Jam", MacWeek, Jan. 10, 1989 p. 1. "Latest--Virtual Memory Draws Nearer", MacWeek, Jan. 31, 1989 p. 1. "First Look--Virtual 2.0 Beats Mac's 8M-Byte RAM Barrier", PC Week, Oct. 23, 1989, pp. 15, 18. Designing Cards and Drivers for Macintosh II and Macintosh SE Apple Computer, Inc., Addison-Wesley Publishing Company, Inc. 1987; ISBN 0-201-19256-X (pp. 1-4 to 1-6). Macintosh Family Hardware Reference Apple Computer, Inc., Addison-Wesley Publishing Company, Inc., 1988; ISBN 0-201-19255-1 (pp. 16-10 and 16-11). MC68020 32-Bit Microprocessor User's Manual (Third Edition), Motorola, Inc., Prentice-Hall, Inc. 1984, 1985; ISBN 0-13-566951-0 (particularly Section 1.3). "Eternal Ramdisk Program", Dec. 06, 1986, CompuServe Information Service. Byte, Nov. 1989, pp. 341-360. "Connectix's Virtual Memory Solution", Macintosh News, Jun. 5, 1989, p. 8. "Mac the Knite"-"No field test for 3-slot '030box2", MacWeek, Nov. 29, 1988, p. 70. MC68030 Enhanced 32-Bit Microprocessor User's Manual (Second Ed.) Motorola, Inc., Prentice-Hall, Inc., 1989, ISBN 0-13-566951-0 (pp. 1-1 to 1-12). MC68851 Paged Memory Management Unit User's Manual; Motorola, Inc., Prentice-Hall, Inc. 1986 ISBN 0-13-566902-2 (particularly Chap. 2 and Appendix C). MC68851 Paged Memory Management Unit User's Manual, Second Ed.; Motorola, Inc., Prentice-Hall, Inc., 1989, ISBN 0-13-566993-6 (as with the first edition, particularly Chap. 2 and Appendix C). Operating Systems Design and Implementation, Andrew S. Tanenbaum, Prentice-Hall, Inc., 1987; ISBN 0-13-637406-9 (Chap. 4). Patent Number 5065306 Issue Date 1991 11 12 Appl. Data 306453 1989 01 27 Assignee Fanuc, Ltd. Inventor(s) Imazeki, Ryoji Kurakake, Mitsuo State/Country JPX Title Serial interchange machine interface circuit Abstract A machine interface circuit for controlling terminal units such as relays, switches and the like of a machine tool through a numerical control unit is disclosed. The machine interface circuit comprises an interchange circuit (11) connected to the numerical control unit (1) through a serial interface; and module circuits (20, 40) connected to the interchange circuit (11) through serial interfaces, each module including a serial/parallel conversion circuit (30, 50) and drivers (21a) and/or receivers (41a). According to the present invention, the machine interface circuit transmits parallel signals over a short distance and includes cables and cable bundles having a simple construction. U.S. Class 364/138 364/DIG2 364/921 364/926.93 364/928 364/929.2 364/932.8 364/933.9 364/935 364/935.2 364/935.3 364/935.42 364/939.5 364/942.3 364/951.1 364/959.1 395/500 IPC G05B 19/18 U.S. Refs 4047003 4071911 4200936 4368511 4628442 4628446 Foreign Refs EPX 198111 0067228 GBX 197912 2038035 Other Refs "Patent Abstracts of Japan", vol. 9, No. 207, Numerical Controller, Aug. 24, 1985. Priority JPX 19870528 62-132806 PCT Number PCT/JP88/00494 PCT Pub. Date 19881201 PCT Pub. No. WO88/09531 PCT Filing Date 19880524 PCT 371 Date 19890127 PCT 102 (e) Date 19890127 Patent Number 5067107 Issue Date 1991 11 19 Appl. Data 229573 1988 11 05 Assignee Hewlett-Packard Company Inventor(s) Wade, Gerald T. State/Country CA Title Continuous computer performance measurement tool that reduces operating system produced performance data for logging into global, process, and workload files Abstract A performance and measurement system for a computing system is presented. Performance data produced by the computing system is collected and reduced before being logged. Once the data is logged, the data may be transported to a workstation and accessed by a user. In the preferred embodiment, the collected and reduced data is logged into three files. The first file is a global data file into which is logged information about the computing system as a whole. The second file is a process data file into which is logged information about selected processes. The third file is a workload data file into which is logged information about classes of processes. Information about processes are logged into the process data file when a process does something "interesting" during a specified interval. For example, a process may be considered to have done something interesting when the process is started, is terminated or uses a predetermined amount of a computing system resource during the specified interval. U.S. Class 395/500 364/DIG1 364/DIG2 364/222.81 364/260.4 364/260.9 364/264 364/264.7 364/267 364/275.5 364/276 364/280 364/281.3 364/282.1 364/283.1 364/285 364/920 364/921.8 364/921.91 364/933.9 364/935 364/935.2 364/940.61 364/940.62 364/942.7 364/946.2 364/949.3 364/949.5 364/951.1 364/962 364/962.1 364/962.3 364/974 364/975.2 364/976 IPC G06F 11/34 G06F 7/14 G06F 15/401 U.S. Refs Re31407 3763474 4015238 4231106 4315311 4322846 4367525 4574351 4606024 4618937 4621319 4713758 4713775 4724525 4730259 4748573 4750106 4750175 4771375 4803683 4829471 4833594 4835680 4843575 4849879 4858152 4922491 4937864 4964129 Patent Number 5068812 Issue Date 1991 11 26 Appl. Data 381548 1989 07 18 Assignee VLSI Technology, Inc. Inventor(s) Schaefer, Thomas J. Shur, Robert D. State/Country CA Title Event-controlled LCC stimulation Abstract A method for simulating a levelized logic circuit including an event-controlled feature for marking components to be reevaluated. An evaluation list is formed which lists signals and corresponding components of the logic circuit which are to be reevaluated. A second list is formed of each component and its corresponding output signals. The external input signals are also listed. Each external input signal is tested for change from a previous evaluation and, if so, the corresponding components in the re-evaluation list are marked for reevaluation. Each component, in levelized order, is then tested to determine whether that component is marked for re-evaluation and, if so, that component is re-evaluated and unmarked, and each signal in the component output signal list which has a non-empty re-evaluation list is tested to determine if the value of the signal has changed since the previous evaluation and, if so, all of the components in that signal's reevaluation list are marked for re-evaluation. Evaluation marks are stored as a marking bit in a memory location associated with a component. The components associated with frequently changing input signals are evaluated without setting or testing their evaluation marks. All reevaluation marks are cleared at the beginning of the execution of the simulation. U.S. Class 364/578 364/488 395/500 IPC G06F 15/18 U.S. Refs 4775950 4815024 4866663 4924429 4945503 4965743 Foreign Refs JPX 198508 60-163141 Other Refs Zeev Barzilai et al.; "HSS-A High Speed Simulator", IEEE Transactions of Computer-Aided Design; July, 1987, pp. 601-617. Patent Number 5068823 Issue Date 1991 11 26 Appl. Data 217616 1988 07 11 Assignee Star Semiconductor Corporation Inventor(s) Robinson, Jeffrey I. State/Country CT Title Programmable integrated circuit using topological and parametric data to selectively connect and configure different high level functional blocks thereof Abstract An apparatus architecture is provided which permits an easily programmed apparatus to serve as an equivalent of an integrated circuit chip, and/or as a building block for a large system. The apparatus is connected to a communications bus which receives apparatus parameter and topological information from a host processor and/or memory. The apparatus includes numerous functional blocks, a core, and a parametric bus. The functional blocks such as serial and parallel ports, D/A and A/D converters, biquad filters, etc. serve to process signal data and are connected in any desired manner through a switching matrix located in the core. The topology of the switching matrix is received via the communication bus. Parameters for the functional blocks are sent to the functional blocks via the communications bus, the core, and the parametric bus. Topological and/or parametric data may be burned into the switch matrix and functional blocks as permanent programmed memory, or held in programmable nonvolatile or volatile memory associated with the core and functional blocks. Signal data is typically received and transmitted via the serial and/or parallel ports and via the D/A and A/D converters (functional blocks) of the apparatus. The signal data is processed extremely quickly by having the parameterized functional blocks perform their operations on the signal data and by forwarding the results to another functional block via the topologically arranged switching matrix. Each apparatus can be made part of a larger wafer-scale system including several identical or architecturally similar apparatus by providing links between the cores of the apparatus. U.S. Class 395/500 364/DIG2 364/926 364/927.8 364/927.92 364/927.93 364/927.95 364/929.1 364/933 364/933.2 364/935 364/935.2 364/935.4 364/942.8 364/943.9 364/943.91 364/944.2 364/948.2 364/948.22 364/949 364/949.4 364/950 364/950.2 364/965 364/965.5 364/965.78 364/965.79 IPC G06F 15/20 G06F 9/00 U.S. Refs 4377849 4467409 4631686 4703436 4786904 4791602 4845633 4855743 4864381 4870302 4896272 4967340 Patent Number 5070445 Issue Date 1991 12 03 Appl. Data 443062 1989 11 28 Inventor(s) Woodward, Thomas R. State/Country PA Title Programmably controlled partially distributed masking mechanism in a programmable unit having variable data path widths Abstract A masker unit in a data processor employed to achieve programmable data path widths for the buses within the processor. A mask generator is provided to partially decode a mask amount from the currently executed control instruction and masking logic is provided with additional decoding logic to complete the mask amount decode. U.S. Class 395/500 364/DIG1 364/244 364/244.6 364/259 364/259.7 364/259.9 364/262.4 364/262.8 364/262.81 IPC G06F 5/00 G06F 13/38 U.S. Refs 4078251 4194241 4466055 4569016 Related Data This application is a continuation, of application Ser. No. 07/328,811, filed Mar. 23, 1989, which is a continuation of co-pending application Ser. No. 07/207,008 filed on June 13, 1988, now abandoned, which is a continuation of co-pending application Ser. No. 881,240 filed on July 2, 1986, now abandoned. Patent Number 5070446 Issue Date 1991 12 03 Appl. Data 654410 1991 02 08 Assignee Thinking Machines Corporation Inventor(s) Salem, James B. State/Country MA Title Method of simulating a hexagonal array of computer processors and/or memories Abstract A method is described for simulating a hexagonal array of computer processors or memories in a computer in which the processor and/or memories are physically connected in a rectilinear grid. The grid provides for communication between adjacent processors in both the horizontal and vertical directions. Thus, it provides physical connections between each processor and four nearest neighbor processors. Each processor is provided with two additional nearest neighbor processors by providing communication between each processor of the array and two additional adjacent processors located on different diagonals in the array. As a result of this arrangement the two additional processors are located either in the same column but in different rows adjacent to the row in which the neighboring processor is located or they are in the same row but in different columns adjacent to the column in which the neighboring processor is located. These additional communication patterns for all the processors add to the rectilinear array a zig zag communication pattern running through the array in either the vertical or horizontal direction. U.S. Class 395/500 364/DIG1 364/228.7 364/231.9 364/232.3 IPC G06F 15/16 G06F 15/76 G06F 15/80 U.S. Refs 4247892 4270170 4493048 4498133 4514807 4621339 4633431 4644496 Other Refs IEEE Transactions on Computers, vol. C-26, No. 5, "The Indirect Binary n-Cube Microprocessor Array" written by M. Pease, III, May 1977, pp. 458-473. Related Data This is a continuation of application Ser. No. 07/275,694, filed Nov. 23, 1988 which is a continuation of Ser. No. 06/825,510, filed Feb. 3, 1986, both are now abandoned. Patent Number 5070474 Issue Date 1991 12 03 Appl. Data 224530 1988 07 26 Assignee Disk Emulation Systems, Inc. Inventor(s) Tuma, George B. Tuma, Wade B. Warne, Robert E. State/Country CA Title Disk emulation system Abstract Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. The disk emulator complies with the SMD interface convention and thus to the central procssor and the SMD disk controller, the disk emulator appears as a disk with virtually a zero access ttime. In one embodiment, the primary systems of the disk emulator are a 66-bit shift register, a parity circuit, a latch circuit, a 66-bit parallel bus and a dynamic random access memory (DRAM) array. Each of these systems interface with control systems of the disk emulator which provide the signals required for the read and write operations of the disk emulator. An error correction process is incorporated in the disk emulator which corrects single bit hard memory errors using only a single parity bit. U.S. Class 395/500 364/DIG1 364/DIG2 364/232.3 364/236.2 364/238.4 364/238.6 364/238.7 364/248.1 364/265 364/267 364/921.8 364/927.8 364/927.81 364/927.92 364/927.93 364/933 364/939 364/940 364/942 364/943.9 364/945 364/947 364/947.6 364/948.4 364/948.5 364/949 364/952 364/952.1 364/959.1 364/963 364/963.3 364/965 364/965.5 364/965.79 364/968 IPC G06F 12/00 U.S. Refs 3863217 3887901 3891959 3891974 4467421 4527234 4617624 4630230 4642759 4727512 4780819 4789960 4849875 Patent Number 5073968 Issue Date 1991 12 17 Appl. Data 230807 1988 08 09 Assignee Hewlett-Packard Company Inventor(s) Morrison, Robert D. State/Country CO Title Method and apparatus for marking emulation analysis states Abstract Additional memory for holding marking tags is used for providing additional information regarding states acquired by an emulator during tracing for dequeueing. The marking tags are determined according to a predetermined coding scheme, loaded in a marking memory, and acquired during tracing along with the fetched instruction states. The combination of addresses, data, status, and the additional marking tags is converted into a list of states which correspond to the test program executed by the target processor means. U.S. Class 395/500 364/DIG2 364/267 364/927.2 364/927.81 364/927.92 364/927.95 364/933 364/933.5 364/933.62 364/933.8 364/939 364/942.8 364/943.9 364/944.92 364/945 364/947 364/947.1 364/957 364/957.1 364/963 364/963.3 364/965 364/965.5 364/976 364/976.1 IPC G06F 11/00 G06F 11/28 U.S. Refs 4205370 4419368 4488228 4598364 4636940 4636941 4694420 4783762 4802165 4835675 Patent Number 5075843 Issue Date 1991 12 24 Appl. Data 368934 1989 06 21 Assignee AT&T Bell Laboratories Inventor(s) Selzer, Gary M. State/Country PA Title Method and apparatus for processing graphical information Abstract Successive graphical segments in a stream of graphical information are processed by first storing each segment within a storage register (12). Thereafter, the stored graphical segment is then acted upon by at least one combinational logic array (16) configured of at least one network (24-1 . . . 24-n), each network being comprised of at least one logic device (26,30). Each logic device performs a prespecified processing operation, such as, for example, a test or a modification, to the stored graphical segment. The prespecified processing operation is dictated by a separate one of a set of rules by which each network is to process the graphical segment. Once the graphical segment has been processed by the logic devices in each of the networks of the combinational logic array, the processed graphical segment is written to an output buffer for subsequent display or storage. U.S. Class 395/500 364/514 IPC G06F 15/62 U.S. Refs 4395700 4432047 4467409 4496944 4725966 4757461 Other Refs Unix System V, Release 2.0 User Reference Manual, AT&T, Nov. 1983. Related Data This application is a continuation of application Ser. No. 067,897, filed on June 29, 1987 now abandoned. Patent Number 5077657 Issue Date 1991 12 31 Appl. Data 367271 1989 06 15 Assignee Unisys Inventor(s) Cooper, Thayne C. Bell, Wayne D. State/Country UT Title Emulator Assist unit which forms addresses of user instruction operands in response to emulator assist unit commands from host processor Abstract An emulator is comprised of a host processor, an emulator, assist unit, and a memory which are closely coupled together over a co-processor bus. Stored in the memory is a user program which is a sequence of instructions from a user instruction set that is to be emulated, and a control program which is a mixture of host processor instructions and emulator assist unit instructions. In operation, the host processor reads and executes the hosts instructions, and it reads and passes the emulator assist unit instructions to the emulator assist unit for execution in that unit. By this means, the host processor and the emulator assist unit share the emulation tasks; and those tasks which are most difficult for the host are performed by the emulation assist unit. As one example the emulator assist unit has registers and controls which respond to the emulator assist unit instructions by examining the fields of the next user instruction that is to be emulated and by generating memory addresses of the operands which that next user instruction operates on; while the host uses those addresses to read the operands from memory and perform operations on the operands as specified by the user instruction. U.S. Class 395/500 364/DIG1 364/DIG2 364/228.6 364/232.3 364/238.2 364/238.5 364/240 364/241 364/244 364/244.9 364/246 364/246.1 364/246.11 364/247 364/247.2 364/247.5 364/247.8 364/251 364/251.3 364/254.4 364/258 364/258.1 364/259 364/259.9 364/261.3 364/261.5 364/262.4 364/262.9 364/280 364/280.2 364/280.8 364/281.9 364/284.4 364/927.81 364/927.96 364/929 364/929.4 364/931.4 364/931.49 364/933 364/933.5 364/933.61 364/941.1 364/946.2 364/957.2 364/975.2 IPC G06F 9/06 G06F 12/06 G06F 1/24 U.S. Refs 3374466 3544969 3646522 3997895 4447876 4514803 4527234 4587612 4591982 4638423 4695945 4729094 4763242 4812975 4859995 4888680 4920481 Patent Number 5079696 Issue Date 1992 01 07 Appl. Data 405543 1989 09 11 Assignee Sun Microsystems, Inc. Inventor(s) Priem, Curtis Malachowsky, Chris State/Country CA Title Apparatus for read handshake in high-speed asynchronous bus interface Abstract Handshake circuitry for an asynchronous bus interface system transferring data between first and second computer systems including apparatus for providing signals to indicate to the second computer system that the first system desires to read data at a specified adress of the second system, apparatus for comparing the specified address with addresses of the second system to provide outputs indicating the time required to retrieve data from the specified address, and apparatus operative in response to the output indicating the time required to retrieve data from the second computer to indicate to the first computer system the time at which the information will be available for transfer to the first computer system. U.S. Class 395/500 364/DIG1 364/DIG2 364/228.4 364/229.2 364/239.9 364/240.8 364/260 364/260.1 364/270.5 364/270.6 364/271.5 364/284 364/284.4 364/931 364/931.4 364/934 364/937 364/940 364/940.81 364/942.2 364/950 364/950.1 364/977.5 395/550 IPC G06A 13/12 U.S. Refs 4809217 Foreign Refs GBX 196801 1098890A GBX 197209 1287657A Patent Number 5083262 Issue Date 1992 01 21 Appl. Data 590327 1990 09 27 Assignee International Business Machines Corporation Inventor(s) Haff, Jr., Lyle E. State/Country NY Title Language bindings for graphics functions to enable one application program to be used in different processing environments Abstract Establishing a language specific linkage between high-level graphics application programs written in a specific programming language and different intermediate-level graphics processors permit a graphics application program to be transported between and used in different graphics processing systems. A single, portable graphics application program can be used with any of the graphics processors with which an application language linkage has been established to produce graphs on an output device. U.S. Class 395/500 364/DIG1 364/DIG2 364/228.3 364/229 364/229.5 364/231 364/231.4 364/231.7 364/234 364/236.2 364/237.2 364/237.3 364/237.7 364/239.9 364/241.9 364/248.1 364/262.4 364/280 364/920.4 364/926.7 364/927 364/927.92 364/928 364/931 364/946.2 364/946.7 364/948.1 364/952 364/952.1 364/977 364/977.1 364/978 IPC G06F 9/45 G06F 15/60 G06F 9/44 U.S. Refs 3558811 3653001 3830962 3893075 4094000 4177514 4414621 4525804 4529978 4539653 4623963 4646228 4649479 4694396 Other Refs IBM Publication entitled "Graphics Development Toolkit", (Aug. 1984), pp. iii-xiii, 1-1 to 1-33. IBM Publication entitled "IBM Personal Computer Graphical File System", (Nov. 1984), pp. iii-xxv. IBM Publication entitled "IBM Virtual Machine/Personal Computer User's Guide", (Dec. 1984), pp. iii-xiii. "GSS-Drivers Assembler Binding Programmer's Guide", Graphic Software Systems, Inc. (Oct. 1984), pp. iii-ix, 1-1 to 1-10. IBM Publication GA37-0014-0 entitled "IBM VM/PC Toolkit-VDI Graphics User's Guide", published Aug. 1985. Related Data This is a continuation of application Ser. No. 06/856,710 filed Apr. 28, 1986, now abandoned. Patent Number 5088033 Issue Date 1992 02 11 Appl. Data 499196 1990 03 23 Assignee Xerox Corporation Inventor(s) Binkley, Joseph H. Caro, Perry A. Dillon, John B. Fay, Charles R. Gibbons, Jonathan Hooks, Hilary N. Kadifa, Abdo G. Lee, Jeffery W. Lynch, William C. Mock, Clayton W. Neely, Everett T. Tallan, Michael L. Thompson, Geoffrey O. Vukkadala, Gaya Wick, John D. Woods, Donald R. State/Country CA Title Data processing system emulation in a window with a coprocessor and I/O emulation Abstract An emulating data processor includes a host system and an emulating processor with outputs to and inputs from the host system. The emulating processor executes sequences of instructions executable by a PC being emulated, but a host processor independently executes sequences of its instructions which are different from PC instructions. Circuitry monitors the emulating processor outputs and provides information to the host system so that it can emulate the environment of the PC CPU, emulating both memory and I/O devices. The memory accesses of the emulating processor are mapped into the host system memory, so that the host processor is protected from defective PC software on the emulating processor. The display updates of the emulating processor are detected and provide information for the host processor in updating a part of its display which provides the information a PC display would provide simultaneously with the display characteristic of the host system. An input/output processor handles I/O operation requests of the emulating processor, using the host system I/O devices to emulate some of the PC I/O devices. Output operations to the printer may go either to a local printer or to a file for subsequent printing, so a buffer which can be unloaded to either destination emulates the PC printer. Floppy operations may be handled either by a floppy disk controller like that of the PC or by a software controller of a file in host rigid disk memory which may be accessed as a PC floppy disk, so that a data structure containing parameters of the operation is loaded and provided to the appropriate controller. Rigid disk operations are handled by another file in host rigid disk memory which may be accessed as a PC rigid disk, and an appropriate I/O operating system routine is provided so that the emulating processor can pass the operation parameters through to the host rigid disk controller in a group of registers. Keyboard input operations may come either from the host keyboard or directly from a data structure managed by the host processor, in each case converted to PC codes, and another buffer which can be loaded from either source emulates the PC keyboard. The host system emulates the environment of the emulating processor while emulating the user interface of the PC. U.S. Class 395/500 364/DIG1 364/222.81 364/228.2 364/228.6 364/231 364/232.3 364/234 364/236.2 364/237.2 364/237.3 364/238 364/238.3 364/238.6 364/238.9 364/239 364/239.6 364/239.9 364/240 364/241.2 364/241.3 364/241.6 364/242.3 364/242.31 364/242.6 364/242.92 364/244 364/244.6 364/247 364/247.2 364/247.8 364/248.1 364/256.3 364/256.6 364/259 364/259.9 364/260 364/260.1 364/261.3 364/261.9 364/262.4 364/262.9 364/264 364/264.3 364/265 364/266.6 364/270 364/271 364/271.2 364/271.5 364/280 364/280.2 364/286.1 364/286.3 IPC G06F 9/455 U.S. Refs 3643252 3932843 3955180 4031517 4149148 4149238 4204206 4253145 4278973 4315310 4365294 4365295 4437184 4456954 4458331 4463442 4484266 4484302 4550386 4555775 4564903 4590556 4591975 4617624 4621319 4648034 4665482 4695945 4703420 4709328 4713751 4716526 4722048 4727480 4727491 4729094 4731736 4757441 4787026 4812975 4833596 4899136 4934036 4939507 Foreign Refs EPX 198512 & SimEPX 0165517 EPX 198601 & SimEPX 0168034 EPX 198610 & SimEPX 0197499 EPX 198612 & SimEPX 0205949 EPX 198702 & SimEPX 0210345 EPX 198705 & SimEPX 0223383 EPX 198707 & SimEPX 0229336 EPX 198707 & SimEPX 0229700 EPX 198709 & SimEPX 0237671 GBX 198311 & SimGBX 2119977 Other Refs Mike Heck "Quadlink Running Apple Software on an IBMPC", Interface Age, May 1984, pp. 108-110. Moskowitz "Applin-Card-Enchancing Your Apple", Interface Age Aug. 1983, pp. 107-108, 111. Morganstein "Alf's 8088 Coprocessor for Your Apple", Byte, Dec. 1984, A. 38, 40-43. Peck "Expanding Your Apple's Applications", Byte, Dec. 1984, pp. A45-A47, A122-126. Libertine, J. A., "The Xerox 16/8 Professional: A Workhorse for the Office", Business Computer Systems, May 1984, pp. 147, 149, 151. Xerox Corporation, "16/8 Professional Computer", one sheet Brochure. Xerox Corporation, "Xerox 16/8 Professional Computer--Two Computers in One--Meeting Leaders Guide", 1-11, 1983. "New Systems Abound at the National Computer Conference", Byte, Jul. 1983, p. 7. "Honeywell MicroSystem 6/10", Honeywell Information Systems CU60-01, 1983. "MicroSystem 6/10", Honeywell Information Systems CU60-04, 1985. "How Would You Design A MicroSystem", Honeywell Information Systems GB 83-00. "Honeywell Introdueces Networking Microcomputer", Honeywell Inc., 1983. "First Public Showing of MicroSystem 6/10 at NCC", Honeywell Inc., 1983. "Honeywell Offers Powerful Networking Microcomputer", Honeywell Inc., 1983. Irwin, J. W., "Use of a Coprocessor for Emulating the PC AT", in F. Waters, Ed., IBM RT Personal Computer Technology, IBM, Austin, 1986, pp. 137-141. Krishnamurty, R., and Mothersole, T., "Coprocessor Software Support", in F. Waters, Ed., IBM RT Personal Computer Technology, IBM, Austin, 1986, pp. 142-146. Goering, R., "Apollo Entry Fuels CAE/CAD Workstation Battle", Computer Design, Mar. 1, 1986, pp. 26-27. "Copydisk", Xerox Corp., Palo Alto, 1980. Rose, C.D., "Apollo Fights Back with New Work Stations", Electronics, Feb. 24, 1986, pp. 20-21. Mace, S. and Sorenson, K., "Amiga, Atari Ready PC Emulators", InfoWorld, vol. 8, No. 18, May 5, 1986. "IBM, Introduces High-Speed, Personal or Multi-User Workstations with New Technology for Technical Professionals", Business Wire, Inc., Jan. 21, 1986. 8010 Star Information System Reference Library, 5.0 Update, Xerox Corporation, 1984, pp. 119-188. "M8.0 Operating System Sofware Bulletin", Xerox Corporation. Seawright, L. H. and Mackinnon, R. A., "VM/370--A Study of Multiplicity and Usefulness", IBM Syst. J., vol. 18, No. 1, 1979, pp. 4-17. Deitel, H. M., An Introduction to Operating Systems, Addison-Wesley, Reading, Mass., 1984, pp. 601-629. Madnick, S. E. , and Donovan J. J., Operating Systems, McGraw-Hill, New York, 1974, pp. 549-563. Smith, D. C., Irby, C., Kimball, R., and Harslem, E., "The Star User Interface: An Overview", AFIPS 1982 National Computer Conference Proceddings. Hall, D. E., Scherrer, D. K., and Sventek, J. S., "A Virtual Operating System", Communications of the ACM, vol. 23, No. 9, Sep. 1980, pp. 495-502. Related Data This is a continuation of application Ser. No. 06/856,526, filed Apr. 28, 1986, now abandoned. Patent Number 5089950 Issue Date 1992 02 18 Appl. Data 397455 1989 08 14 Assignee Fanuc Ltd Inventor(s) Miyata, Mitsuto Matsumura, Teruyuki Nagashima, Noritake State/Country JPX Title Part profile input method Abstract A method for inputting a part profile which includes a standard or repeating shape. If a pattern profile input is requested at the time of a part profile input operation, a profile menu is displayed in a software key area (13b). When a pattern profile is selected by the profile menu, the selected pattern profile, e.g., a pattern view (CGP) of a series of grooves is displayed in conversational screen display area (13a) and a message (DQS) calling for various dimensions is displayed. The profile of the series of grooves is specified based on data entered in response to the message. U.S. Class 364/191 364/DIG1 364/234 364/237.2 364/237.3 364/244 364/244.6 364/260.4 364/260.9 364/286.1 364/286.2 364/474.22 395/100 395/500 IPC G05B 19/403 G06F 3/153 G06F 15/40 U.S. Refs 4490781 4513366 4788636 4868761 4901220 4928221 Foreign Refs JPX 198207 121443 Priority JPX 19871217 62-319388 PCT Number PCT/JP88/01260 PCT Pub. Date 19890629 PCT Pub. No. WO89/06004 PCT Filing Date 19881213 PCT 371 Date 19890814 PCT 102 (e) Date 19890814 Patent Number 5093776 Issue Date 1992 03 03 Appl. Data 367297 1989 06 15 Assignee Wang Laboratories, Inc. Inventor(s) Morss, Stephen Dreyfus, Boris State/Country MA Title Information processing system emulation apparatus and method Abstract For use in an information processing system 10, the system including a system bus 16 having a system address bus 16a and a system data bus 16b and at least two data processors 12 and 14 coupled to the system bus, emulation apparatus for enabling a first one of the data processors to execute, in conjunction with a second one of the data processors, a program requiring access to predetermined address locations associated with a specific type of device, typically an I/O device. The specific type of device is either not resident within the system or is resident at different address locations. The emulation apparatus includes circuitry 30 for detecting an occurrence of an access cycle by the first data processor to the predetermined address location, circuitry 50 for halting the first data processor before completion of the access cycle and circuitry 50 for notifying the second data processor that the first data processor is halted. The emulation apparatus further includes circuitry 24a for indicating to the second data processor a value of the predetermined address location being accessed and a type of access to the predetermined address location. The second data processor includes circuitry for interpreting the address value and type of access, for accessing a corresponding address location having a same type of specific device or a corresponding type of device and for causing the first data processor to be released to complete the access cycle. U.S. Class 395/500 364/DIG1 364/229 364/230.6 364/232.3 364/232.8 364/234 364/237.3 364/240.2 364/241.9 364/244.6 364/247.2 364/255.1 364/259.9 364/927.81 IPC G06F 9/00 U.S. Refs 3938101 3955180 4031517 4313162 4315321 4447876 4482948 4484266 4509122 4547849 4590556 4638423 4665501 4675813 4727480 4875186 4920481 Foreign Refs EPX 198601 0168084 EPX 198612 0205949 EPX 198707 0260568 Patent Number 5097407 Issue Date 1992 03 17 Appl. Data 302150 1989 01 25 Assignee Integrated Inference Machines Inventor(s) Hino, James H. Walsh, John M. State/Country CA Title Artificial intelligence processor Abstract A high-speed processor capable of processing any user-selected one of several symbolic languages is disclosed. The processor includes a programmable instruction decoder and a store for a ram-variable instruction set. Fixed bit length tags precede and identify the type of data associated with each tag. Large groups of bits in one or more tags are decoded simultaneously to access a programmable microsequencer and a microprogram memory. U.S. Class 395/375 364/DIG1 364/229.5 364/230.5 364/238.3 364/238.4 364/239 364/239.7 364/240 364/240.5 364/242 364/242.2 364/243.4 364/243.41 364/244.3 364/245.5 364/245.6 364/245.7 364/251.4 364/254 364/254.5 364/255.1 364/255.5 364/255.7 364/259.9 364/261.3 364/261.5 364/261.9 364/262.4 364/262.7 364/262.8 364/262.9 364/274 364/274.1 364/275.1 364/275.8 364/276.4 364/277 395/500 395/800 IPC G06F 9/16 U.S. Refs 3725868 3766532 4126896 4156279 4586127 4922414 Related Data This invention, which is a continuation of 06/894,907 filed Aug. 8, 1986, now abandoned, relates generally to computer architecture and more specifically to a computer processor having efficient symbolic processing and self test capability. Patent Number 5097412 Issue Date 1992 03 17 Appl. Data 184395 1988 04 21 Assignee Hitachi, Ltd. Inventor(s) Orimo, Masayuki Mori, Kinji Suzuki, Yasuo Kawano, Katsumi Koizumi, Minoru Nakai, Kozo Kasahima, Hirokazu State/Country JPX Title Method for simulating the operation of programs in a distributed processing system Abstract In a distributed processing system wherein a plurality of processors are connected by a transmission medium; a simulation method for a distributed processing system characterized by defining transmission delay times ascribable to the transmission medium, input/output data items and processing times of respective programs which are set in the system, and numbers of the processors in which the programs are stored. U.S. Class 395/500 364/DIG1 364/228.3 364/230 364/231.4 364/231.6 364/232.3 364/237.2 364/237.3 364/262.4 364/262.9 364/264 364/264.3 364/265 364/271.5 395/800 IPC G06F 11/34 U.S. Refs 3648253 3678467 3763474 3766524 4149243 4183083 4262331 4315315 4393446 4403286 4405982 4466063 4486829 4495562 4517641 4583222 4677587 4698751 4703481 4740895 4769772 4814978 4837676 4845665 4866663 4972314 Other Refs Encyclopedia of Computer Science and Engineering by A. Ralston and E. Reilly, pp. 563, 564, Van Nostrand Reinhold Pub., 2nd ed., 1983. Priority JPX 19870424 62-99754 Patent Number 5097437 Issue Date 1992 03 17 Appl. Data 217542 1988 07 17 Inventor(s) Larson, Ronald J. State/Country MN Title Controller with clocking device controlling first and second state machine controller which generate different control signals for different set of devices Abstract A controller for controlling a microprocessor-based system incorporates two cooperatively operating state machine controllers and is capable of interfacing with bus and memory subsystems while maintaining synchronous handshake with more than one type of microprocessor on a bus which may operate at a different speed than the system memory subsystems and peripheral devices. The controller provides functional and timing parameters to satisfy requirements for an asynchronous bus and for more than one type of device which reside on the bus. U.S. Class 395/775 364/DIG1 364/DIG2 364/228.6 364/231 364/238.3 364/238.4 364/238.6 364/238.9 364/239.9 364/240 364/240.2 364/240.8 364/240.9 364/241.9 364/242.3 364/242.31 364/242.6 364/247 364/247.2 364/259 364/259.9 364/263 364/270 364/270.3 364/271 364/926.1 364/926.2 364/926.6 364/926.9 364/926.91 364/926.92 364/926.93 364/927.92 364/927.93 364/927.97 364/931.5 364/935.4 364/937 364/939 364/939.4 364/939.6 364/940 364/940.6 364/940.71 364/940.81 364/941.5 364/942.08 364/942.1 364/942.6 364/942.79 364/942.8 364/950 364/950.3 364/950.5 364/964.9 364/968 395/500 IPC G06F 9/00 G06F 13/10 U.S. Refs 4590551 4779089 4805137 4831520 4843544 4864496 4989203 4993023 Other Refs J. Theus et al, "Futurebus anticipates coming needs", Electronics International, Jul. 1984, New York, pp. 108-112, vol. 57. D. M. Taub, "Arbitration and Control Acquisition in the Proposed IEEE 896 Futurebus", IEE Micro, vol. 4, No. 4, Aug. 84, pp. 28-41. "VME bus requester releases bus four ways", Electrical Design News, vol. 2, No. 8, Aug. 1985, pp. 241-242. Patent Number 5097533 Issue Date 1992 03 17 Appl. Data 277372 1988 11 29 Assignee International Business Machines Corporation Inventor(s) Burger, Brian H. Hidalgo, Domingo S. State/Country TX Title System and method for interfacing computer application programs written in different languages to a software system Abstract A support system and method for interfacing of computer application programs written in a plurality of languages to a software system such as a database manager of the like. A plurality of generic application program interfaces or entry points are defined having a corresponding plurality of parameters in a consistent form required by the system to execute functions. The parameters are transformations of like parameters associated with the application programs which call the APIs. Processor states corresponding to threads in the application programs are stored in a table shared by the generic APIs. Upon return from the call and execution of the system function, processor state is restored and control returned to the application program. Necessity for separate entry points for applications written in each different supported language is thereby avoided as well as associated increased development effort, maintenance, and support. U.S. Class 395/500 364/DIG1 364/226.4 364/228.1 364/239.9 364/244 364/244.3 364/247 364/247.8 364/260.4 364/260.9 364/270.5 364/270.9 364/280 364/280.9 364/282.1 364/284 364/286 364/286.3 IPC G06F 7/10 U.S. Refs 3665421 4493027 4667290 4787035 4905138 4961133 Other Refs "General Purpose Interface for Extending APL", IBM Technical Disclosure Bulletin, 10-71, p. 1559. "Centaur: The System", P. Borras et al., Institute of National Recherche Inf. Autom., Le Chesnay, France, Dec. 1987, Report No. 777. Patent Number 5101491 Issue Date 1992 03 31 Appl. Data 146672 1988 01 21 Inventor(s) Katzeff, Kurt State/Country SEX Title System means for synthesizing, generating and checking software for a computer Abstract A synthesizer means for generating software for a computer which is programmed for controlling a physical system. The software generated by the synthesizer represents a new function to be incorporated in the existing system. The synthesizer includes a device for receiving a formal description representative of the new function in a specification language and for translating the specification into a base document. The base document is further processed by document processing devices for handling the static, interface and dynamic parts of the description to produce an error-free base document. The complete base document is translated by an information processing device into an internal code document which is used by a check device and a simulation device. A compiling device translates the internal code document into an intermediate code document suitable for input to said computer. U.S. Class 395/500 364/DIG1 364/221 364/225.6 364/226.1 364/226.4 364/231 364/232.3 364/234 364/242.4 364/262.4 364/262.9 364/274 364/274.1 364/274.2 364/274.5 364/275.6 364/280 364/280.4 364/281.3 364/281.7 364/282.1 364/286.1 364/286.4 364/917.96 IPC G06F 9/64 G06F 9/455 G06F 15/16 U.S. Refs 3930237 4204253 4205371 4231087 4315315 4437184 4500963 4536840 4580228 4631664 4635189 4734854 4734856 Foreign Refs EPX 108408 0116694 EPX 198603 0172980 Other Refs Busnello et al., "Structure of a Source Program Generator", IBM TOB vol. 14, No. 1, pp. 306-311. Wisniewski, "Aids for VLSI Design Entry and Partitioning", IEEE International Conference on Circuits and Computers, IEEE, 1982. Waters, R. C., "The Programmer's Apprentice: Knowledge Based Program Editing", IEEE Transactions on Software Engineering, vol. SE-8, No. 1, Jan. 1982. Dell et al., "Computer-Aided Design for Software", Software and Microsystems, vol. 1, No. 1, Oct. 1981. Priority SEX 19830819 8304501 Related Data This application is a continuation in part of application Ser. No. 06/929,031, filed Nov. 10, 1986, now abandondeed, which is also a continuation of application Ser. No. 06/642,165, filed Aug. 20, 1984, now abandoned. Patent Number 5107417 Issue Date 1992 04 21 Appl. Data 255603 1988 10 11 Assignee NEC Corporation Inventor(s) Yokoyama, Yasushi State/Country JPX Title Address translating method for translating virtual address to real address with specified address register to allow bypass of translation steps Abstract An address converting method for use in a data processor with a virtual memory. The method includes a step for generating effective addresses by the use of address registers, and a step for deciding whether or not an operating mode which is defined for each process is in an activated state. The method also includes a step responsive to a positive determination at the previous step for determining whether or not an address register having a specific reference number was used in the generation of the effective addresses, and a step responsive to a negative determination at the foregoing step for converting an effective address into a physical address. Furthermore, the method includes a step which is responsive to a positive decision of the step determining register use for treating the effective address generated as a physical address, and a step for accessing a memory by the physical address resulting from the conversion step or that from the physical address step. U.S. Class 395/500 364/DIG1 364/247 364/247.2 364/247.8 364/255.1 364/255.8 364/256.3 364/256.5 IPC G06F 13/00 G06F 9/30 G06F 12/8 U.S. Refs 3723976 3902164 4296468 4320456 4374417 4551797 4612612 4631660 4654777 4682281 4691282 4757447 4769770 4774653 4785398 4835734 Priority JPX 19871008 62-252362 Patent Number 5107442 Issue Date 1992 04 21 Appl. Data 665257 1991 03 06 Assignee Recognition Equipment Incorporated Inventor(s) Weideman, William E. State/Country TX Title Adaptive neural network image processing system Abstract A neural-simulating system for processing input stimuli includes a plurality of layers, each layer receives layer input signals and generates layer output signals, the layer input signals include signals from the input stimuli and ones of the layer output signals from only previous layers within the plurality of layers. Each of the plurality of layers includes a plurality of neurons operating in parallel on the layer input signals applied to the plurality of layers. Each of the neurons derives neuron output signals from a continuously differentiable transfer function for each of the neurons based upon a combination of sets of weights associated with the neurons and the layer input signals. An adaptive network is associated with each neuron for generating weight correction signals based upon gradient estimate signals and convergence factors signals of each neuron and for processing the weight correction signals to thereby modify the weights associated with each neuron. An error measuring circuit generates relative powered error signals for use in generating the gradient estimate signals and the convergence factors signals. U.S. Class 395/11 382/15 395/22 395/24 395/500 IPC G06F 15/18 U.S. Refs 4941122 Other Refs A Neural Network for Visual Pattern Recognition; IEEE Computer; K. Fukushima; Mar. 1988; pp. 65-75. Related Data This application is a divisional of U.S. patent application Ser. No. 07/453,588, filed Dec. 20, 1989, and entitled "Variable Gain Neural Network Image Processing system" which is a continuation-in-part of U.S. patent application Ser. No. 07/296,520, filed Jan. 12, 1989, and entitled "Neural Network Image Processing System" and now U.S. Pat. No. 4,941,122 issued Jul. 10, 1990. Patent Number 5109503 Issue Date 1992 04 28 Appl. Data 355266 1989 05 22 Assignee GE Fanuc Automation North America, Inc. Inventor(s) Cruickshank, Ancil B. Davis, Richard K. State/Country VA Title Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respectively define plurality of predetermined counters Abstract A reconfigurable counter is provided which includes first and second memories coupled via a common bus to a microprocessor which controls the process of configuring and reconfiguring the counter. A programmable hardware array, coupled to the microprocessor, is capable of being programmed to emulate a plurality of different counter types. The first memory stores a plurality of different counter configuration profiles, each of which corresponds to a different type counter configuraiton. In one or more of the selected counter types, different counter modes such as an up-down counter mode, pulse direction counter mode and A quad B counter modes are available. When the user indicates a selected counter profile to the microprocessor, the microprocessor writes the corresponding counter configuration profile from the first memory into the programmable hardware array using the parameters or modes of operation stored in the second memory until such time as the user indicates the choice of another counter profile to the microprocessor. U.S. Class 395/500 364/DIG1 364/DIG2 364/231 364/232.9 364/234 364/239 364/239.8 364/239.9 364/240 364/240.1 364/243 364/244 364/244.6 364/244.8 364/244.9 364/247 364/247.1 364/247.8 364/251 364/251.3 364/263 364/264 364/264.7 364/921.8 364/921.9 364/927.81 364/927.92 364/927.93 364/927.94 364/928 364/928.5 364/933 364/933.1 364/933.7 364/935 364/935.2 364/935.4 364/935.42 364/939 364/939.7 364/942.7 364/946.2 364/946.9 364/948.1 364/949 364/949.2 364/949.4 364/964 364/965 364/965.76 364/965.77 IPC G06F 15/60 U.S. Refs 4031517 4674089 4751671 4924382 4964056 Other Refs Xilinx Technical Data, XC3000 Logic Cell.TM. Array Family, Copyright 1988. Patent Number 5109504 Issue Date 1992 04 28 Appl. Data 458939 1989 12 29 Assignee Texas Instruments Incorporated Inventor(s) Littleton, James G. State/Country TX Title Graphics program adaptor Abstract An adapter for modifying graphics software programs at load time. The invention is a process, which may be part of a hardware or firmware configuration used with a computer system, and which scans the program for selected instructions representing routines to be replaced with a substitute routine. If such an instruction is encountered, the instruction is replaced with an interrupt trap. The substitute graphics routine is located at an address stored at the interrupt trap location. U.S. Class 395/500 364/261 364/946.7 IPC G06F 9/00 U.S. Refs 4028684 4400798 4542453 4566004 4751703 4769767 4791558 4819234 4858114 4866665 4870406 4924413 4954941 Patent Number 5111423 Issue Date 1992 05 05 Appl. Data 222565 1988 07 21 Assignee Altera Corporation Inventor(s) Kopec, Jr., Stanley J. Chan, Yiu-Fai Hartmann, Robert F. State/Country CA Title Programmable interface for computer system peripheral circuit card Abstract A programmable interface for a peripheral circuit card is provided. The card is intended for use with a particular computer bus architecture, and the interface can be customized by a user for a particular card design. Instead of designing a custom interface chip, the designer can program one or more programmable logic devices on the interface chip to interface with whatever devices are on the peripheral circuit card. U.S. Class 395/500 364/DIG1 364/DIG2 364/238.3 364/238.5 364/239 364/239.1 364/239.8 364/242.6 364/242.92 364/244.6 364/244.9 364/247 364/247.8 364/927.8 364/927.92 364/927.93 364/927.95 364/927.97 364/927.99 364/932.8 364/933 364/933.7 364/935 364/935.2 364/935.4 364/935.41 364/939 364/939.3 364/940.81 364/941 364/942.3 364/942.4 364/942.8 364/947 364/947.1 364/947.2 364/947.4 364/949 364/949.2 364/950 364/950.3 364/952 364/952.1 364/965 364/965.76 IPC G06F 13/00 U.S. Refs 3566153 4006466 4034354 4124899 4127896 4144561 4156796 4179738 4188665 4225919 4254473 4334157 4390963 4393443 4395754 4442502 4443845 4453229 4473878 4485439 4488256 4570220 4580240 4587609 4591981 4609986 4617479 4625308 4638451 4670748 4670855 4675808 4701878 4727977 4751671 4794558 4825054 4853846 4920483 Foreign Refs GBX 198306 0080823 Other Refs Bursky, D., "One chip integrates all IBM PS/2 Micro Channel control needs", Electronic Design, vol. 36, No. 9, Apr. 1988, pp. 67-69. International Business Machines Corporation, "MicroChannel.RTM. Architecture Specification". International Business Machines Corporation, "IBM.RTM. Personal System/2.RTM. Seminar Proceedings". Altera Corporation, "Altera User-Configurable Adapter Interface Chips for PS/2 Micro Channel-EPB2001, EPB2002", Rev. 1.0. Patent Number 5113516 Issue Date 1992 05 12 Appl. Data 388281 1989 07 31 Assignee North American Philips Corporation Inventor(s) Johnson, Brian C. State/Country CT Title Data repacker having controlled feedback shifters and registers for changing data format Abstract A data repacker utilizing a multiplexer, one intermediate register, two shifters, and a control for these circuits. The multiplexer output is connected to the intermediate register, which has a storage length greater than the size of data words to be repacked. The first shifter receives the output of the register, and its output can be concatenated with an input data word to form one input to the multiplexer. The output of the register is provided as another input to the multiplexer. The second shifter also receives the output of the multiplexer, and has an output which is the repacker output. Information representing the number of bits in and the number of bits out is used to determine the most and least significant bits of the intermediate data which will be stored in the intermediate register, and to control the shifters. U.S. Class 395/500 341/60 341/87 364/239.3 364/259.6 364/260.6 364/260.7 364/715.01 364/947.6 364/951.1 364/965.7 IPC G06F 3/00 G06F 5/01 H03M 7/00 H03M 7/30 U.S. Refs 3638195 3930232 4131940 4141005 4291370 4430711 4467443 4506345 4595911 4667305 4845668 4885584 4963867 Other Refs Terry A. Welch; "A Technique For High-Performance Data Compression"; Computer Jun. 1984, pp. 8-19. Patent Number 5113517 Issue Date 1992 05 12 Appl. Data 469722 1990 01 24 Assignee Xerox Corporation Inventor(s) Beard, Marian H. Caro, Perry A. Hsiao, Jennifer B. Mackey, Kevin J. Sandman, Jr., James G. Steinbach, Gary R. Woods, Donald R. State/Country CA Title Concurrent display of data from two different processors each having different display font and user interface for controlling transfer of converted font data therebetween Abstract A multiprocessor system comprises concurrent display of video data reflecting the operation of two processors in discrete portions of a single display screen with a user interface adapted for interaction with both processors. One processor controls the entire display while allocating a portion of the display screen for the use of the other processor which processor emulates a target processor system, for example, the IBM PC. A user interface is represented on the display screen in the form of metaphoric objects, called icons, with which the user can interact by changing the input focus to a designated object by visually pointed to it via the input means, which thereafter permits manipulation of the designated object of interaction with data input/output relative to the designated object. This input means is also used to initially change the input focus to either the allocated emulating processor screen portion or to the remaining portion of the central processor display screen prior to interaction with the metaphoric objects in a selected screen portion, the change of the input focus causing subsequent user input via the input means to be directed to the selected screen portion until interrupted by a change in focus input to the other of the screen portions by the user via the input means. An icon may be a representation of a virtual object, such as a virtual floppy disk, that is accessible in either the host system world or in the emulating processor world even though the virtual floppy disk may have a filing system alien to the host system world. Facilities are also provided to permit transferring of displayed data reflecting the operation of one processor to the control of the other processor in response to user inputs selecting the data to be transferred and indicating the destination of the selected data on the display. More specifically, if data from each processor is displayed in a discrete portion of the display screen, the user may select data in one processor's controlled screen portion and transfer it to the other processor's controlled screen region, and vice versa. U.S. Class 395/500 340/721 364/DIG1 364/228 364/232.1 364/232.3 364/234 364/235 364/236.2 364/237.2 364/239 364/241.9 364/242.94 364/242.95 364/252 364/253 364/253.2 364/260.2 364/260.4 364/280 364/280.2 364/286 364/286.3 395/155 395/162 395/800 IPC G06F 3/153 G06F 15/16 G06F 5/00 U.S. Refs 3643252 3932843 4149148 4149238 4204206 4253145 4278973 4315310 4365295 4437184 4456954 4458331 4463442 4484266 4484302 4545015 4550386 4555775 4564903 4574364 4604710 4617624 4621319 4642759 4787026 4792896 4833596 4849878 4868738 Foreign Refs EPX 198512 0165517 EPX 198601 0168034 Other Refs Dissertation of David Canfield Smith, "Pygmalion: A Creative Programming Environment", Chapter 4 & 5, pp. 93-166, May, 1975. "Xerox's `Star`--Word Processing, `Typesetting`, Documentation, Business Graphics, Multi-Level Math, Electronic Communication and More All Come Together in a Revolutionary New Video Terminal Workstation", The Seybold Report, vol. 10, No. 16, Apr. 27, 1981. "Accessing Files on Emulated PC Disks at a Host Computer", IBM TDB, vol. 28, No. 6, Nov. 1985, pp. 2752-2754. "M8.0 Operating System Software Bulletin", Xerox Corporation. Madnick, Stuart E. et al., "Operating Systems", McGraw-Hill Book Company, 1974, pp. 549-563. Hall, Dennis E., et al., "A Virtual Operating System", Communications of the ACM, vol. 23, No. 9, Sep. 1980, pp. 495-502. Deitel, Harvey M., "An Introduction to Operating Systems," Addison-Wesley Publishing Company, Inc., Revised First Edition, Jul. 1984, pp. 601-629. Irwin, J. W., "Use of a Coprocessor for Emulating the PC AT", in F. Waters, Ed., IBM RT Personal Computer Technology, IBM, Austin, 1986, pp. 137-141. Krishnamurty, R., and Mothersole, T., "Coprocessor Software Support", in F. Waters, Ed., IBM RT Personal Computer Technology, IBM, Austin, 1986, pp. 142-146 Huntzinger, No. 223,383, May 27, 1987. Goering, R., "Apollo entry fuels CAE/CAD workstation battle", Computer Design, Mar. 1, 1986, pp. 26-27. "Copydisk", Xerox Corp., Palo Alto, 1980. Rose, C. D., "Apollo Fights Back with New Work Stations", Electronics, Feb. 24, 1986, pp. 20-21. Mace, S. and Sorenson, K, "Amiga, Atari Ready PC Emulators", InfoWorld, vol. 8, No. 18, May 5, 1986. 8010 Star Information System Reference Library, 5.0 Update, Xerox Corporation, 1984, pp. 119-188. David C. Smith, et al., "The Star User Interface: An Overview", Proceedings of the National Computer Conference, Houston, TX, Jun. 7-10, 1982, pp. 515-528. David C. Smith et al., "Designing the Star User Interface", Byte Magazine, vol. 7(4), 15-28, Apr. 1982. Related Data This is a continuation of application Ser. No. 07/170,958, filed Mar. 24, 1988, now abandoned which was a division of application Ser. No. 856,525, filed Apr. 28, 1986, now U.S. Pat. No. 4,899,136. Patent Number 5115502 Issue Date 1992 05 19 Appl. Data 246046 1988 09 19 Assignee Tektronix, Inc. Inventor(s) Tallman, James L. State/Country OR Title Method and apparatus for determining internal status of a processor using simulation guided by acquired data Abstract A method and apparatus for determining the internal state of a processor without disturbing the operational environment of the processor employs a two phase process. In the first phase, external signals produced by the processor in the execution of a known program are monitored and recorded for subsequent analysis. In the second phase, the recorded information is analyzed in the light of the known characteristic of the processor, the program it was executing, and the signals recorded during the first phase. The internal state of the processor is thereby determined after the execution of each instruction. In addition, provisions are made for the specification of breakpoints, and the examination of simulated status of the processor on the occurrence of the breakpoints. U.S. Class 395/500 364/DIG1 364/232.3 364/232.8 364/237.2 364/240 364/244 364/244.6 364/247 364/252 364/259 364/259.3 364/264 364/264.1 364/264.3 364/264.6 364/276 371/16.1 IPC G06F 11/00 U.S. Refs 3644936 3707725 3763474 3937938 4080650 4275441 4293950 4312066 4429368 4470893 4482953 4503536 4520440 4521849 4542505 4581738 4635193 4636940 4674089 4748556 4763288 4796258 4802165 4813009 Related Data This is a division of application Ser. No. 06/667,687 filed Nov. 2, 1984, now U.S. Pat. No. 4,813,009. Patent Number 5119465 Issue Date 1992 06 02 Appl. Data 368716 1989 06 19 Assignee Digital Equipment Corporation Inventor(s) Jack, Martin L. Gumbel, Richard T. State/Country NH Title System for selectively converting plurality of source data structures through corresponding source intermediate structures, and target intermediate structures into selected target structure Abstract A data structure format conversion system comprising a front end converter, a back end converter, and a converter executive. The front end converter converts a source data structure in a source format to data in an intermediate format. The back end converter converts the data in the intermediate format to a target data structure in a target format. Finally, a converter executive controls the front end converter and back end converter to effect a conversion from the source data structure in the source format to the target data structure in the target format, through the intermediate format. U.S. Class 395/500 364/DIG1 364/232.3 364/235 364/237.2 364/239 364/274 364/274.1 364/274.8 364/280 364/280.2 364/280.4 364/282.1 364/282.3 364/282.4 364/283.2 364/286 364/286.3 IPC G06F 9/44 G06F 9/45 U.S. Refs 4667290 4751740 4754428 4791558 Other Refs Stephen Mallinson, "IBM Communications--Architectures and Directions," Proceedings of the Int'l Conf. on Networking Technology and Architectures, London, Jun. 1988, pp. 49-60. Word Perfect for IBM Personal Computers and PC Networks, "Convert Program," Word Perfect Corporation, Orem, Utah (1990), pp. 91-99. Patent Number 5121491 Issue Date 1992 06 09 Appl. Data 571329 1990 08 22 Assignee Sun Microsystems, Inc. Inventor(s) Sloan, Robert Evans, David State/Country CA Title MIDI to RS 232 interface Abstract An interface which includes a MIDI send terminal having first and second pins for providing an output signal, an RS 232 terminal having first and second pins for receiving a signal from the MIDI send terminal, apparatus for coupling any MIDI output signal to the RS 232 terminal, the apparatus for coupling including apparatus for shifting a base level at which the signals are presented at the MIDI terminal to a base level at which the signals are received at the RS 232 terminal, apparatus for shifting the voltage swing of signals presented at the MIDI terminal to a voltage swing at which the signals are received at the RS 232 terminal, and apparatus for disabling the RS 232 terminal if a device to which the RS 232 terminal is connected would normally respond in an undesirable manner to unexpected data received on the RS 232 terminal. U.S. Class 395/500 84/645 395/275 IPC G06F 3/00 U.S. Refs 4662261 4700604 4744281 4768412 4776253 4945806 5011412 5025701 Patent Number 5121492 Issue Date 1992 06 09 Appl. Data 021302 1987 03 02 Assignee Meridian Data, Inc. Inventor(s) Saville, III, Winthrop L. Klein, Raymond Meyer, Frederick P. Prussian, Michael P. State/Country CA Title System for simulating access times of a CD ROM on a hard disk by slowing the operation of the hard disk Abstract A simulation system for simulating transfer operation of blocks of data in a target data storage unit such as an optical compact disk read only memory. Blocks of the data are contained in a memory to which a simulation computer has direct access without requiring that the target data storage unit be operatively connected to the simulation computer. Simulation comprises the steps of characterizing a hypothetical transfer of data operation of the target data storage unit by calculating its performance characteristics for the particular transfer operation in units of time; controlling direct access by the simulation computer to the data in the memory in accordance with the calculated performance time, and providing the results of the direct access simulation to the user. Simultaneous simulations of the target data storage unit may be carried out for the same or different types of host computers. U.S. Class 395/500 364/232.3 364/249.6 364/260 364/271.4 364/927.81 364/950.4 364/952.31 IPC G06F 9/455 G06F 12/02 G06F 13/00 U.S. Refs 4499536 4511963 4660106 4775969 4953122 Patent Number 5125088 Issue Date 1992 06 23 Appl. Data 672748 1991 03 21 Assignee Compaq Computer Corporation Inventor(s) Culley, Paul R. State/Country TX Title Computer system speed control at continuous processor speed Abstract A personal computer is disclosed having a high speed microprocessor which executes in a variety of selectable speed modes to provide greater compatibility with application programs written for slower speed microprocessors. A logic means is included responsive to a speed select signal which does not change the speed of the microprocessor oscillator (clock) but rather changes the length of a wait state or "STOP" state of the microprocessor. In the STOP state the microprocessor (CPU) does not run bus cycles until the timer times out thereby releasing the CPU STOP. By varying the length of the time delay of the one-shot timer, the microprocessor simulates microprocessor speed changes which have the appearance of earlier generation computers with older microprocessors. A logic means permits a computer operator to select a speed which the operator wants the microprocessor to "simulate" and also permits the operator to select a type of older microprocessor which the operator wants the new high speed microprocessor to "simulate." A means of automatically varying the apparent microprocessor speed is also disclosed when data transfer from a floppy diskette are detected. U.S. Class 395/500 395/550 IPC G06F 15/00 U.S. Refs 4050096 4366540 4502117 4507732 4547849 4631702 4787032 Other Refs "8257/8257-5 Programmable DMA Controller," Intel Corporation, 1974; pp. 6-115 to 6-131. IBM Technical Disclosure Bulletin, vol. 15, No. 1, Jun. 1972, pp. 111-113. Related Data This is a continuation of co-pending application Ser. No. 331,065 filed on Mar. 28, 1989, which is a continuation of co-pending application Ser. No.904,982 filed on Sep. 8, 1986. Patent Number 5127095 Issue Date 1992 06 30 Appl. Data 193270 1988 05 11 Assignee Minolta Camera Kabushiki Kaisha Inventor(s) Kadono, Takashi State/Country JPX Title Addressing system for a memory unit Abstract In a system including a main body for processing data and a memory detachably provided to the main body, an addressing method for addressing the memory to write data therein or to read data therefrom being that plural bits of an address to be applied to the memory from the main body are divided into two parts, one part of address bits is transmitted to the memory through an address line provided for addressing the memory while another part of address bits is transmitted to the memory through a data line provided for communicating data between the main body and the memory, and two parts of address bits are joined in the memory to access the memory by full bits of the address. U.S. Class 395/425 364/DIG1 364/DIG2 364/235 364/235.7 364/239 364/244 364/244.6 364/955 364/955.6 364/961.1 395/500 395/550 IPC G06F 13/00 G06F 3/00 U.S. Refs 4050058 4112480 4144562 4213177 4232366 4345244 4467447 4559615 4613943 4622546 4626985 4675808 4675830 4698749 4805092 4849875 4868784 4882702 Priority JPX 19870514 62-117941 Patent Number 5129077 Issue Date 1992 07 07 Appl. Data 464681 1990 01 16 Assignee Thinking Machines Corporation Inventor(s) Hillis, W. Daniel State/Country MA Title System for partitioning a massively parallel computer Abstract A method and apparatus are described for improving the utilization of a parallel computer by allocating the resources of the parallel computer among a large number of users. A parallel computer is subdivided among a large number of users to meet the requirements of a multiplicity of databases and programs that are run simultaneously on the computer. This is accomplished by dividing the parallel computer into a plurality of processor arrays, each of which can be used independently of the others. This division is made dynamically in the sense that the division can readily be altered and indeed in a time sharing environment may be altered between two successive time slots of the frame. Further, the parallel computer is organized so as to permit the simulation of additional parallel processors by each physical processor in the array and to provide for communication among the simulated parallel processors. These simulated processors may also be stored, in virtual memory. As a result of this design, it is possible to build a parallel computer with a number of physical processors on the order of 1,000,000 and a number of simulated processors on the order of 1,000,000,000,000. Moreover, since the computer can be dynamically reconfigured into a plurality of independent processor arrays, a device this size can be shared by a large number of users with each user operating on only a portion of the entire computer having a capacity appropriate for the problem then being addressed. U.S. Class 395/500 364/DIG1 364/228.2 364/229 364/230 364/232.1 364/232.8 364/235 364/238 364/239 364/240 364/241.9 364/242.94 364/242.95 364/243 364/243.1 364/243.4 364/243.41 364/244 364/244.9 364/246 364/246.3 364/247 364/248.1 364/252 364/253 364/253.2 364/254 364/254.6 364/258 364/259 364/259.1 364/265 364/266 364/270 364/270.2 IPC G06F 13/00 U.S. Refs 4247892 4523273 4598400 4639857 4644496 4722084 4733353 4748585 Other Refs Ian R. Greenshields, "Dynamically Reconfigurable, Yector-Slice Processor", IEEE Proceedings, vol. 129, Pt. E, No. 5 (Sep. 1982), pp. 207-215. Lin et al."Reconfiguration Procedures for a Polymorphic and Partitionable Multiprocessor." IEEE Transactions on Computers, vol. C-35, No. 10 (Oct. 1986), pp. 910-915. Tsutomu Hoshino "An Invitation to the World of PAX." IEEE Computer, (May 1986), pp. 68-80, 0018-9162/86/0500-0068$01.00. Charles L. Seitz, "The Cosmic Cube", Communications of the ACM, vol. 28, No. 1 (Jan. 1985), pp. 22-33. Preparata et al. "The Cube-Connected Cycles: A Versatile Network for Parallel Computation." Communications of the ACM, vol. 24, No. 5 (May 1981), pp. 300-309. Hillis W. D. "Chapter 4 The Prototype." In: The Connection Machine (Massachusetts, MIT, 1985), pp. 71-90, 145-172. NCR45CG72 GAPP Application Note No. 3, Ohio, NCR Corporation, 1985, pp. 1-23. NCR45CG72, Ohio, NCR Corporation, 1984, pp. 1-12. Hillis, W. D. "The Connection Machine", Massachusetts, MIT (1981), pp. 1-21, 23-29. A.I. Memo No. 646. Kenneth E. Batcher "Design of a Massively Parallel Processor." IEEE Transactions on Computers, vol. C-29, No. 9 (Sep. 1980), pp. 836-840. Asbury et al. "Concurrent Computers Ideal for Inherently Parallel Problems." Computer Design, (Sep. 1, 1985), pp. 99-102, 104, 106-107. Related Data This is a continuation of Application Ser. No. 07/323,173, filed Mar. 15, 1989, now abandoned, which is a continuation of Application Ser. No. 06/902,290, now abandoned, filed Aug. 29, 1986 and is also a continuation-in-part of Application Ser. No. 07/184,739, now U.S. Pat. No. 5,008,815, filed Jun. 27, 1988, which is a continuation of Application Ser. No. 06/499,474, now U.S. Pat. 4,814,973, filed May 31, 1983. Patent Number 5131089 Issue Date 1992 07 14 Appl. Data 413803 1989 09 28 Assignee GRiD Systems Corporation Inventor(s) Cole, James F. State/Country CA Title Solid state disk drive emulation Abstract A system for causing a computer solid state memory to emulate a magnetic disk mounted in a disk drive. In the preferred embodiment, the system includes two removable RAM cards and two ROM's. Program instructions encoded in firmware in the system BIOS translate disk service requests from software running on the computer into appropriate commands and addresses on the RAM cards or on the ROM. The system permits software written for use with floppy disks to be used with solid state memory devices such as RAM cards or ROM without modification of the software. U.S. Class 395/500 364/232.3 364/254.8 364/255 395/425 IPC G06F 12/00 G06F 9/455 U.S. Refs 4295205 4476526 Foreign Refs GBX 198208 2093236 GBX 198609 2172126 Related Data This application is a continuation-in-part of application Ser. No. 07/365,147 for a Hand Held Computer filed Jun. 12, 1989, and assigned to the same assignee as the present invention. This invention relates to a system and method for enabling solid state computer memory devices (such as RAM cards, ROM's and EPROM's) to be accessed as though they were a magnetic disk in a disk drive attached to the computer. Patent Number 5133062 Issue Date 1992 07 21 Appl. Data 566743 1990 08 13 Assignee Advanced Micro Devices, Inc. Inventor(s) Joshi, Sunil P. Iyer, Venkatraman State/Country CA Title RAM buffer controller for providing simulated first-in-first-out (FIFO) buffers in a random access memory Abstract A RAM buffer is provided for managing the address inut lines of a RAM buffer to simulate the operation of two FIFO's therein. In addition, an apparatus is provided for allowing random access by a node processor in a local area network node using the RAM buffer controller to manage transmit and receive FIFO's to have random access to any address in the address space of the buffer without restriction to FIFO boundaries. Also disclosed is an apparatus for transmitting packets from said buffer organized into one or two linked lists. Further, an apparatus is provided for allowing independent initialization of any of the pointers in the RAM buffer controller which are not currently selected, and for allowing software requests for read or write access by the node processor. Further, an apparatus and a method are provided for recording status and length information at the end of a packet instead of in front thereof and for allowing any incoming packet to be flushed without saving status information or to be flushed while saving its status information. U.S. Class 395/500 364/DIG1 364/231 364/231.8 364/232.3 364/236.2 364/236.3 364/238 364/238.3 364/238.4 364/238.6 364/238.9 364/239 364/239.51 364/239.6 364/240 364/240.8 364/241.9 364/242.3 364/242.6 364/242.94 364/242.95 364/242.96 364/244 364/244.3 364/247 364/247.2 364/247.7 364/247.8 364/248.1 364/248.2 364/251 364/251.3 364/252 364/254 364/254.5 364/256.3 364/259 364/259.2 364/259.9 364/262.4 364/262.9 364/264 364/264.6 364/270.5 364/271 364/281.3 364/281.4 364/284 364/284.3 364/285 IPC G06F 12/00 G06F 12/10 U.S. Refs 3493935 3676846 4203154 4220990 4334287 4334287 4435780 4482956 4499576 4507760 4535420 4569041 4590468 4612636 4642797 4698753 4744023 4949301 Foreign Refs DEX 197706 2629498B1 FRX 198212 8209912 WOX 198012 WO80/02755 WOX 198403 WO84-00835 WOX 198403 WO84/00836 Other Refs Steve Landry, Electronic Design, Printer Buffer Proves RAM-Based Logic's Strength And Versatility, Nov. 14, 1985, pp. 139-144. A. C. Parket and A. W. Nagle, "Hardware/Software Tradeoffs in a Variable World Width, Variable Queue Length Buffer Memory," pp. 159-164. IBM Technical Disclosure Bulletin, "Enqueue-Top for Recovery," vol. 24, No. 1A, Jun. 1981. Related Data This application is a division of application Ser. No. 06/836,936, filed Mar. 6, 1986, now U.S. Pat. No. 4,949,301. Patent Number 5133063 Issue Date 1992 07 21 Appl. Data 223612 1988 07 25 Assignee Hitachi, Ltd. Inventor(s) Naito, Ichiro Maezawa, Hiroyuki State/Country JPX Title Method and system for outputting program change effect information to a user Abstract A program change effect indicating method for use in a computer system designed to support the determination of parts to be changed in a program. Change steps associated with the method include; the steps of generating analyzed program information by analyzing a program, the analyzed program information representing attributes of respective statements in the program which constitute the program as well as connections between the statements; generating, in accordance with predetermined program intention determining rules, program intention information representing the intentions of the respective statements in the program from the analyzed program information. Inputting change designating information designated by a user which represents a statement to be changed and the contents of the changes; Further change steps associated with the method includes generating, in accordance with predetermined change detail determining rules, change effect information which identifies statements to be changed in association with the change designated by the user and the contents of the required changes from the program intention information, the information representing the relationship between the statements, and the change designating information; and outputting the change effect information. U.S. Class 395/500 364/DIG1 364/191 364/234 364/237.2 364/237.3 364/243 364/262.4 364/262.9 364/274 364/274.1 364/274.2 364/274.3 364/274.5 395/50 395/922 IPC G06F 15/40 U.S. Refs 4635189 4670834 4805113 4827428 4862349 Other Refs R. C. Waters "The Programmer's Apprentice: Knowledge Based Program Editing", IEEE Tran. on Software Engineering, vol. SE-8, No. 1, Jan. 1983 pp. 1-12. R. C. Waters "The Programmer's Apprentice: A Session with KBEmacs", IEEE Tran. on Software Engineering, vol. SE-11, No. 11, Nov. 1985, pp. 1296-1320. Priority JPX 19870729 62-187658 Patent Number 5134701 Issue Date 1992 07 28 Appl. Data 310153 1989 02 10 Assignee Hewlett-Packard Co. Inventor(s) Mueller, David C. Williams, Steven R. Abu-Jbara, Nabil M. State/Country CO Title Test apparatus performing runtime replacement of program instructions with breakpoint instructions for processor having multiple instruction fetch capabilities Abstract The test apparatus for monitoring the operation of a processor that has multiple instruction fetch capability monitors the instruction memory to record the sequence of program instructions that are retrieved by the processor from program memory. The test apparatus determines when a jump operation is executed and determines the target of the jump oepration by inserting a break point instruction in place of one of the two program instructions that is retrieved by the processor from program memory. This instruction substitution is accomplished by an instruction jamming circuit that forces the break point instruction onto the processor data bus as part of the program instruction fetch cycle in lieu of one of the instruction retrieved as part of the execution of the jump instruction. If the break point operation is executed, then the target address of the jump operation is the address location that contains the break point instruction that was substituted for one of the program instructions retrieved from the instruction memory. In this case, the test apparatus responds to the execution of the break point instruction by replacing the program instruction originally retrieved from program memory and substituted for by the break point instruction. Thus, the break point instruction acts as a flag to indicate that this address is the target address of the jump instruction. If the break point instruction is not executed by the processor, it is because the jump instruction target address is the location that contains the other retrieved program instruction. U.S. Class 395/500 364/DIG2 364/264 364/264.4 364/267 364/267.2 371/19 IPC G06F 11/30 U.S. Refs 3509541 3904860 4080650 4126893 4176394 4241416 4429368 4495563 4511960 4511961 4571677 4635193 4740895 4782461 4811345 4819234 4910663 Other Refs "Custom Trigger Chip Speeds 32-Bit Emulator To 33 MHz and Beyond"; Novellino; Electronic Design; Jan. 26, 1989; pp. 77 and 78. Patent Number 5134702 Issue Date 1992 07 28 Appl. Data 854380 1986 04 21 Assignee NCR Corporation Inventor(s) Charych, Harold Chattopadhya, Sandip State/Country NY Title Serial-to-parallel and parallel-to-serial converter Abstract A serial-to-parallel and parallel-to-serial data format converter has a plurality of first-in, first-out (FIFO) buffer memory devices, an input circuit for receiving serial data bits, an output circuit for outputting serial data bits and a clocking circuit for clocking selected ones of the data bits into and out of selected ones of the FIFO buffer memory devices. The clocking circuit clocks serial data bits either into or out of each of the FIFO buffer memory devices at a rate slower than the rate of the receipt of the serial data bits by the input circuit, or the rate of the outputting of serial data bits by the output circuit, respectively. U.S. Class 395/500 364/DIG2 364/238 364/239 364/239.2 364/244.3 364/926.1 364/926.2 364/926.9 364/926.91 364/926.92 364/933 364/933.3 364/935 364/935.4 364/935.52 364/939.2 364/939.5 364/939.7 364/942.1 364/950 364/950.5 364/951 364/960.2 364/960.7 364/968 395/250 IPC G06F 5/00 U.S. Refs 3946379 4048625 4125870 4151609 4165541 4216460 4284953 4298936 4375078 4377806 4404426 4409587 4425562 4426685 4429300 4447804 4482956 4486854 4497041 4586159 4620180 4674064 4696498 4734850 4750149 4764894 Patent Number 5138706 Issue Date 1992 08 11 Appl. Data 312903 1989 02 21 Assignee Compaq Computer Corporation Inventor(s) Melo, Maria L. Walker, Karl N. State/Country TX Title Password protected enhancement configuration register for addressing an increased number of adapter circuit boards with target machine emulation capabilities Abstract A computer system is provided which is compatible with existing programmable option select systems and which provides optional enhanced system setup capabilities. The enhanced system permits use of application software designed specifically for existing programmable option select systems which utilize limited system configuration data registers but further provides an optional mode accessed during system setup procedures wherein application software can access and utilize an expanded set of system setup configuration registers to enhance the performance of the computer system. U.S. Class 395/500 364/DIG2 364/916 364/926.1 364/927.81 364/931 364/931.11 364/933 364/933.2 364/939.5 364/947 364/947.1 364/947.3 364/964 364/975.2 364/976 395/800 IPC G06F 9/455 U.S. Refs 4177452 4218740 4453211 4453229 4661991 4791602 4815031 4859995 4885482 4970504 4984213 4991085 Other Refs IBM Corp., Personal System/2 Model 80 Technical Reference, First Edition, Apr. 1987, pp. 2-29 to 2-51. "Eisa vs. Microchannel: Multimastering is the Key", Electronic Design, vol. 36, No. 23, 13 Oct. 1988, pp. 38-40. Patent Number 5140687 Issue Date 1992 08 18 Appl. Data 415375 1989 09 27 Assignee Texas Instruments Incorporated Inventor(s) Dye, Thomas A. Roskell, Derek Simpson, Richard Asal, Michael Guttag, Karl M. Tebbutt, Neil Van Aken, Jerry State/Country TX Title Data processing apparatus with self-emulation capability Abstract A microprocessor, specially adapted for graphics processing applications, and which has a self-emulation capability by which the contents of its internal registers may be dumped or loaded to or from external memory on an instruction-by-instruction basis, is disclosed. The microprocessor has circuitry which is responsive to an emulate enable signal, or to a predetermined instruction code, so that normal execution is halted at the end of the ion, with execution jumping to a predetermined vector. Responsive to a dump signal, the microprocessor begins execution of a routine which presents a predetermined series of memory addresses on a memory bus, in conjunction with the contents of registers internal to the microprocessor. Accordingly, the addressed locations of a memory device connected to the memory bus can be written with the register contents, for subsequent interrogation by the user. Similarly, responsive instead to a load command, a routine is executed which presents the series of addresses to the memory bus and loads the internal registers with the data values presented on the memory bus. The load feature is similarly utilized by the user's loading of the addressed memory locations with the desired contents of the internal registers. A system containing a microprocessor constructed according to the invention may be configured so that the emulate enable signal is generated by the control signals generated by the microprocessor upon each instruction fetch from the external memory. U.S. Class 395/500 IPC G06F 15/62 U.S. Refs 4441154 4623962 4628467 4638423 4674089 4675833 4731742 4785416 4809167 Related Data This application is a continuation of application Ser. No. 06/948,337, now abandoned, filed Dec. 31, 1986, which is continuation-in-part of application Ser. No. 790,299 filed Oct. 22, 1985, now abandoned. Patent Number 5142469 Issue Date 1992 08 25 Appl. Data 501612 1990 03 29 Assignee GE Fanuc Automation North America, Inc. Inventor(s) Weisenborn, Gerald M. State/Country VA Title Method for converting a programmable logic controller hardware configuration and corresponding control program for use on a first programmable logic controller to use on a second programmable logic controller Abstract A method is provided for converting a hardware configuration and corresponding control logic program for use on a first programmable logic controller (PLC) to an equivalent hardware configuration and control logic program for use on a second PLC. A graphic representation of hardware modules which are usable with the first PLC are displayed for the user's consideration. The user selects those modules which are actually employed in a particular hardware configuration for the first PLC and a first hardware configuration file is created therefrom. A determination is then made of those second PLC hardware modules which are equivalent to the first PLC hardware modules contained in the first hardware configuration file. This determination is made by referencing a first data base which includes information as to which hardware modules for use on the second PLC are equivalent to corresponding hardware modules for use on the first PLC. A mapping of I/O points from the first PLC to I/O points of the second PLC is then generated. These determining and generating a mapping steps define the second hardware configuration of the second PLC. The method further includes generating a second control program for use with the second PLC from the statements of the first PLC and the mapping of I/O points. This is accomplished by checking each statement of the first control program with a second data base to determine an equivalent statement for the second control program. U.S. Class 364/146 364/DIG2 364/147 364/926.9 364/949 364/949.2 364/949.4 364/951.1 364/972 364/972.2 395/500 395/919 395/921 395/922 IPC G06F 9/06 G06F 15/60 U.S. Refs 4250563 4504927 4677548 4849928 5038317 Patent Number 5142622 Issue Date 1992 08 25 Appl. Data 304696 1989 01 31 Assignee International Business Machines Corporation Inventor(s) Owens, Gary L. State/Country CA Title System for interconnecting applications across different networks of data processing systems by mapping protocols across different network domains Abstract The system and method of this invention automatically routes a connection between data processing systems in different network domains. As an example, an application running on a data processing system utilizing a network domain such as TCP (Transmission Control Protocol), can automatically make a connection to another data processing system utilizing a different network domain such as SNA (Systems Network Architecture). The connection is automatically performed in the layer containing the communication end point objects. In a preferred embodiment, the connection is automatically performed in the socket layer of the AIX operating system, or in the socket layer of other operating systems based upon the Berkeley version of the UNIX operating system. U.S. Class 395/200 364/DIG1 364/229 364/229.5 364/232.3 364/239.9 364/242.5 364/242.94 364/242.96 364/280.9 364/284 364/284.3 364/284.4 395/500 395/700 IPC G06F 13/12 U.S. Refs 4274139 4322792 4415986 4500960 4530051 4575793 4586134 4604686 4612416 4631666 4677588 4679189 4703475 4706081 4736369 4760395 4768150 4790003 4811216 4825354 4831518 4849877 4855906 4882674 4893307 4901231 Other Refs Introducing the UNIX System by H. McGilton and R. Morgan pp. 1-7 McGraw-Hill Software Series. The UNIX Book by Mike Banahan and A. Rutter, J. Wiley & Sons Inc. 1983 pp. 107-120. The Design of the UNIX Operating System, by Bach, M. J., 1986, Prentice Hall, Englewood Cliffs, N.J. Dictionary of Computing, 8th Ed., Mar. 1987, IBM Document Composition Facility pp. 238, 326. Data Communications, vol. 16, No. 5, May 1987, New York, US, pp. 120-142, "SNA to OSI: IBM Building Upper-Layer Gateways" by Thomas J. Routt. The Sixth International Phoenix Conference on Computers and Communications Feb. 25, 1987, Scottsdale, Ariz., USA, pp. 354-360 by R. Martinez et al. IEEE Micro, vol. 5, No. 2, Apr. 1985, New York, US, pp. 53-66, "A Multimicrocomputer-based Structure for Computer Networking" by A. Faro et al. IEEE Infocom '87, Proceedings, Sixth Annual Conference, Mar. 31, 1987, San Francisco, Calif., USA, pp. 1045-1052, "Gateways for the OSI Transport Service" by G. V. Bochman et al. Proceedings, Ninth Data Communications Symposium, Sep. 10, 1985, Whistler Mountain British Columbia, pp. 2-8 "Development of a TCP/IP for the IBM/370" by R. K. Brandiff et al. Patent Number 5142672 Issue Date 1992 08 25 Appl. Data 132296 1987 12 15 Assignee Advanced Micro Devices, Inc. Inventor(s) Johnson, William M. Olson, Timothy A. Dutton, Drew J. Lee, Sherman Stoenner, David W. State/Country CA Title Data transfer controller incorporating direct memory access channels and address mapped input/output windows Abstract Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the above transfer function in a manner that facilitates communication between the first and second set of devices from the compartively lower performance of the second set of devices. According to the preferred embodiment of the invention, a data transfer controller i.e., ("DTC") is disclosed that includes a set of direct memory access ("DMA") channels and an input/output controller comprising a set of address mapped I/O ports. Both the DMA channels and I/O ports may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus"). The resulting DTC interface between the Local Bus and a Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance. U.S. Class 395/500 364/DIG1 364/238.3 364/239 364/239.1 364/239.3 364/240 364/240.2 364/240.5 364/241.9 364/284 364/284.1 364/284.2 IPC G06F 13/28 U.S. Refs 3940743 4309754 4313160 4568930 4821185 4847750 4851990 4947366 Foreign Refs EPX 198305 0079140 EPX 198612 0204960 Other Refs 8167 Computer Design, vol. 21, Feb. 1982, No. 2, pp. 121-126 "Dual-Bus Design For A Microcomputer", Robert A. Garrow. 2119 E. D. N. Electrical Design News, vol. 27, Mar. 1982, No. 5, pp. 117-125 "Eliminate System Growth Pains With A .mu.P/Controller Interface" by D. L. Ruhberg and M. C . Wood. Nachrichtentechnik Elektronick--29 (1976) H., vol. 25, pp. 229-232, "Mehrmikrorechnersysteme mit Registerkopplung" by W. Cimande and A. Tschelebiev. Patent Number 5146572 Issue Date 1992 09 08 Appl. Data 593606 1990 10 04 Assignee International Business Machines Corporation Inventor(s) Bailey, Roger N. Mansfield, Robert L. State/Country TX Title Multiple data format interface Abstract An interface circuit for providing an interface with the parallel data bus that transfers information in a multiple of formats. The interface includes a control circuit that receives or sends control signals from or to the parallel bus to regulate the data transfer and to specify one of the plurality of formats. An addressing circuit, connected to the control circuit, is provided for computing addresses for each of the data received or sent according to the specified format. An accessing circuit connected to the bus, control and address circuits is provided to store or retrieve data from or to the bus according to the computed data addresses. This interface provides a means to serialize data when, in one format, the first word of a data transfer is provided on one part of the data bus but, in a second format, the first data word is provided on another part of the data bus. U.S. Class 395/425 365/230.02 365/230.05 395/400 395/500 IPC G06F 12/00;1 G11C 8/00 U.S. Refs 4041472 4047157 4120048 4195342 4205373 4245307 4296469 4309754 4317168 4354256 4370712 4371925 4432055 4447878 4559620 44586131 4610004 4729118 4742487 4747070 4847759 4893280 4916658 Foreign Refs EPX 198606 0206083 EPX 198707 0254648 Other Refs IBM Technical Disclosure Bulletin, vol. 28, No. 1, Jun., 1985, pp. 20-23, "Dual Port, Dual Data Width Random-Access Memory Controller". Related Data This is a continuation of application Ser. No. 07/273,286 filed Nov. 17, 1988, now abandoned. Patent Number 5146582 Issue Date 1992 09 08 Appl. Data 368449 1989 06 19 Assignee International Business Machines Corp. Inventor(s) Begun, Ralph M. State/Country FL Title Data processing system with means to convert burst operations into memory pipelined operations Abstract A data processing system includes a microprocessor operable in a burst mode to read data from a memory. The memory, its controller and bus are operable in a pipelining mode. Array logic is connected between the microprocessor and the remaining elements for converting the burst mode to the pipeline mode. U.S. Class 395/500 364/DIG2 364/927.93 364/927.97 364/927.98 IPC G06F 13/00 U.S. Refs 3710348 4360891 4509113 4716545 4802085 4807183 4851990 5019965 5029124 Other Refs "80386 Hardware Reference Manual", Intel Corp., 1986, Chaps. 1-2, pp. 3/14-3/17. "i486 Microprocessor," Intel Corp., 1989, Sections 2.0, 6.1, 6.2.7, and 7.2-7.2.7. Patent Number 5146583 Issue Date 1992 09 08 Appl. Data 734113 1991 07 24 Assignee Matsushita Electric Industrial Co., Ltd. Inventor(s) Matsunaka, Masahiko Nishiyama, Tamotsu Ueda, Masahiko State/Country JPX Title Logic design system for creating circuit configuration by generating parse tree from hardware description language and optimizing text level redundancy thereof Abstract An apparatus and method for translating a function description of a circuit presented in hardware description language includes parsing the function description of the circuit to generate a parse tree. The structure of the parse tree is deformed to optimize the test level redundancy of the function description to thereby generate a deformed parse tree. The deformed parse tree is then translated into function blocks representing a hardware configuration of the circuit set forth by the function description. U.S. Class 395/500 364/DIG1 364/221.2 364/221.8 364/489 395/921 IPC G06F 15/20 U.S. Refs 4703435 4791356 4803636 4816999 4817029 Priority JPX 19870925 62-241289 JPX 19880315 63-61081 Related Data This application is a continuation of now abandoned application, Ser. No. 07/249,554 filed on Sep. 26, 1988. Patent Number 5150474 Issue Date 1992 09 22 Appl. Data 344614 1989 04 28 Assignee NEC Corporation Inventor(s) Kaneko, Takashi State/Country JPX Title Method for transferring arguments between object programs by switching address modes according to mode identifying flag Abstract In computer systems, a flag identifying the address mode of a first computer system is stored into a parameter list of a calling object program together with an argument quantity value when the calling object program is generated by the first computer system from a calling source program. The addresses of arguments as specified by the argument quantity value are stored into other word locations of the parameter list. When a called object program is executed by a second computer system, the mode identifying flag is detected from the parameter list of the calling object program, and the addresses of the arguments stored in the parameter list are referenced in an address mode specified by the flag and the referenced arguments are transferred from the calling object program to the called object program. U.S. Class 395/500 364/DIG1 364/280.1 364/280.4 395/700 IPC G06F 9/45 U.S. Refs 4241399 4330822 4338663 4736320 4736321 4787034 4791558 4992971 5097533 Other Refs Pyster, A. B., Compiler Design and Construction, pp. 281-313 (1980). Gries, D., Compiler Construction for Digital Computers, pp. 187-192 (1971). Priority JPX 19880429 63-105954 Patent Number 5151984 Issue Date 1992 09 29 Appl. Data 631186 1990 12 20 Inventor(s) Newman, William C. Titchener, Paul F. Powell, Douglas B. State/Country CA Title Block diagram simulator using a library for generation of a computer program Abstract An apparatus and/or method using an automatic program generation computer for generation of a computer program which represents a functional system on a display. A system has a plurality of interactively connected functionality blocks which form a block diagram and typically, the block diagram has one or more feedback loops. Each of the blocks has at least one input, at least some of the blocks have at least one input functionally defined by and connected to at least one of the outputs. At least one of the blocks is a state block whose operation at one time is dependent on the condition of at least one input for the state block at a prior time. A stored update state procedure is provided corresponding to the state block defining the state as a function of at least one of the inputs to the state block. At least one stored update output procedure is provided and corresponds to each of the blocks for defining at least one of the outputs of a block. The output of the update output procedure is a function of at least one of the inputs of a block and/or the state of a block. U.S. Class 395/500 364/221.2 364/933.8 IPC G06F 15/00 U.S. Refs 3971100 4315315 4385367 4389706 4455619 4546435 4570217 4584642 4615011 4656603 4677587 4694411 4710863 4727473 4754410 4758953 4796194 Other Refs Fashano, M., "Communication System Simulation and Analysis with SYSTID", IEEE Journal on Selected Areas in Communications, vol. SAC-2, No. 1, pp. 8-29, Jan. 1984. Messerschmitt, D. G., "A Tool for Structured Functional Simulation", IEEE Journal on Selected Areas in Communication, vol. SAC-2, No. 1, pp. 137-147, Jan. 1984. Messerschmitt, D. G., "Blosim-A Block Simulator", pp. 1-48, Jun. 7, 1982. Modestino, J. W. et al., "Interactive Simulation of Digital Communication Systems", IEEE Journal on Selected Areas in Communication, vol. SAC-2, No. 1, pp. 51-75, Jan. 1984. Poza, H. B. et al., "A Wideband Data Link Computer Simulation Model", Computers and Electrical Engineering, vol. 5, No. 2, pp. 135-149, Jun. 1978. Shanmugan, K. S. et al., "Computer-Aided Modeling, Analysis and Design of Communication Systems-Introduction and Overview", IEEE Journal on Selected Areas in Communications, vol. SAC-2, No. 1, pp. 1-8, Jan. 1984. University of Kansas and TRW, "BOSS (Block Oriented Systems Simulator) User's Manual, BOSS Version: Star 1.1", 1987. Wade, W. D. et al., "Interactive Communication Systems Simulation Model-ICSSM", IEEE Journal on Selected Areas in Communications, vol. SAC-2, No. 1, pp. 102-128, Jan. 1984. "Grafcet as a Description and Simulation Tool at the Functional Level in CAD System*", Diane Boucher et al., 1984. "Designscope", BrainPower, Inc. (USA), Apr. 1986. "Graphical Function Chart Programming for Programmable Controllers", Control Engineering, Oct. 1985. "The Time-Sequenced Adaptive Filter", Earl R. Ferrara, Jr. et al., (IEEE) 1981. "Block-Oriented Systems Simulator (BOSS)", K. Sam Shanmugan, et al. (IEEE) 1986. Desoer et al., Basic Circuit Theory (1969), p. 508. Kopec, "The Signal Representation Language SRL", IEEE Transactions on Acoustics, Speech and Signal Processing, vol. ASSP-33, No. 4 (1985). Kopec, "The Integrated Signal Processing System ISP", IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. ASSP-32, No. 4, (1984). Guernic, et al., "Signal-A Data Flow -Oriented Language for Signal Processing", IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. ASSP-34, No. 2, (1986). Related Data This application is a continuation of U.S. patent application Ser. No. 07/173,771, filed Mar. 23, 1988, now abandoned which is a continuation-in-part of U.S. patent application Ser. No. 07/065,372, filed Jun. 22, 1987, now abandoned the priority of both are claimed herein. Patent Number 5151985 Issue Date 1992 09 29 Appl. Data 518307 1990 04 27 Assignee Apple Computer, Inc. Inventor(s) Sander, Wendell Sander, Brian State/Country CA Title Disk drive controller Abstract The invented controller uses a programmable parameter scheme which makes it possible to read and write 3 1/2 inch variable and fixed speed drives, as well as standard 5 1/4 inch drives. Additionally, the present invention uses a plus/minus rate multiplier to correct for symmetry and frequency errors. Also provided is a form of read post compensation which corrects for peak shift effects on disks with insufficient precompensation. Other advanced features of the present invention include the use of half clock circuits to provide half clock resolution in the signal being written to and read from the disk and the capability of operating at continuously variable clock speeds and data rates dynamically programmable by the computer. U.S. Class 395/500 364/DIG1 364/232.2 364/236.2 364/239 364/239.3 364/245 364/245.5 IPC G06F 3/00 G06F 13/10 U.S. Refs 4281356 4393458 4495533 4509118 4558375 4716475 4742448 4789975 Foreign Refs GBX 197012 1214737 GBX 197108 1242576 GBX 197406 1357949 GBX 197506 1397317 GBX 197511 1415584 GBX 197602 1424268 GBX 197703 1466915 Related Data This is a continuation of application Ser. No. 055,443 filed May 28, 1987, now abandoned. Patent Number 5155836 Issue Date 1992 10 13 Appl. Data 325170 1989 03 17 Inventor(s) Jordan, Dale A. Fitzsimmons, Lynne A. Greenseth, William A. Hoffman, Gregory L. Stubbs, David D. State/Country OR Title Block diagram system and method for controlling electronic instruments with simulated graphic display Abstract A block diagram editor system and method is implemented in a computer workstation that includes a CRT and a mouse, graphics and windowing software, and an external communications interface for test instruments. The computer is programmed for constructing, interconnecting and displaying block diagrams of functional elements on the CRT. From prestored routines for each functional element, the software assembles and executes a program that emulates the functional operations of each element and transfers data from output from each element in turn to an input of a succeeding block, as determined by the block diagram configuration. The block functions include signal generating and analysis functions, and functions for control of various types of test instruments, which can be interactively controlled through the CRT and mouse. The computer converts desired outputs of the instruments into control settings and receives, analyzes and displays data from the instruments. Blocks can also be grouped into macroblocks. U.S. Class 395/500 364/232.3 364/488 IPC G06F 15/60 U.S. Refs 4064394 4315315 4389806 4399502 4443861 4455619 4546435 4656603 4663704 4677587 4723209 4725971 4730315 4812996 4813013 4831524 4901221 Foreign Refs EPX 198710 87303122.3 Other Refs Wolfe, "Block Diagrams and Icons Alleviate the Customary Pain of Programmming GPIB Systems", Electronic Design, Apr. 17, 1986, 7 pages. Related Data This is a continuation of application Ser. No. 07/007,234 filed Jan. 27, 1987 and issued of Sept. 19, 1989 as U.S. Pat. No. 4,868,785. Patent Number 5155837 Issue Date 1992 10 13 Appl. Data 317919 1989 03 02 Assignee Bell Communications Research, Inc. Inventor(s) Liu, Cheng-Chung Lo, Daniel S. Nazif, Zaher A. Wu, Fu-Lin Zobre, Donald W. State/Country NJ Title Methods and apparatus for software retrofitting Abstract A time-shared computer system is disclosed in which computer software programs, either application programs or operating system programs, can be retrofitted with new programs which are totally incompatible with the old versions, all without interrupting service provided by the software programs. In a real time software system such as one providing telephone service, the processor (or processors in a multiprocessor system) is divided into two logical partitions. The old version of the software runs in one partition while the new version is loaded into and started up in the other partition. When the new version is verified to be properly operating, the data traffic is transferred from the old version parition to the new version partition in two steps. First the input data is switched to the new verison. When the transactions in progress in the old version are all completed, the output data is switched from the old version to the new version. This software retrofitting on the fly is disclosed in connection with a telephone transaction processing system used to support special telephone services such as dial 800 calls and credit card calls. U.S. Class 395/500 364/DIG1 364/232.3 364/242.94 364/265 364/285 364/933.8 364/943.9 364/962.1 371/4 IPC G06F 9/00 G06F 15/00 G06F 11/00 U.S. Refs 4558413 4788637 4809170 5008814 Other Refs "Life Cycle Support and Update of No. 4 ESS Software", E. A. Davis et al., IEEEE Document No. 0536-1486/82/0000-0216, p. 5G5.1, 1982. Patent Number 5155838 Issue Date 1992 10 13 Appl. Data 344603 1989 04 28 Assignee Kabushiki Kaisha Toshiba Inventor(s) Kishi, Minoru State/Country JPX Title Computer system with emulation mechanism Abstract A computer system with an emulation mechanism includes a program execution unit for executing an application program. The application program includes a write command. An emulation control unit writes an address and data concerning a write command in buffers in response to the write command. When a predetermined condition is satisfied, the emulation control unit generates and outputs an interrupt to the program execution unit. In response to the interrupt, the program execution unit executes an emulation program and emulates the address and data stored in the buffers upon execution of the emulation program. U.S. Class 395/500 364/DIG2 364/927.2 364/927.81 364/939.2 IPC G06F 3/153 G06F 5/00 U.S. Refs 4649479 4835685 4860246 4975829 Other Refs Tanenbaum, A., Operating Systems, 1987, pp. 110-123. IBM Technical Reference, 6936763. IBM Technical Reference, Options and Adapters vol. 2, 6137806. Priority JPX 19880428 63-106260 JPX 19880430 63-108465 JPX 19880930 63-245929 Patent Number 5155839 Issue Date 1992 10 13 Appl. Data 414376 1989 09 29 Assignee Allen-Bradley Company, Inc. Inventor(s) Weppler, Robert C. State/Country OH Title Apparatus using in undifferentiated strobe output to interface either of two incompatible memory access signal types to a memory Abstract A node adapter chip for linking a node microprocessor to a serial data link incorporates a read/write circuit and an interrupt processing means to allow increased flexibility in connecting the adapter to different node microprocessors with different interface protocols. The read/write input circuit accepts dual strobe or single strobe type read/write commands and the interrupt processor accepts either conventional interrupt handling or "polled" operation for use with microprocessors that do not have interrupt capabilities. A flag multiplexer allows the controller in the node adapter to receive status information from a serial interface in the adapter without the need for extra data transfer cycles. U.S. Class 395/500 364/DIG1 364/DIG2 364/239.9 364/927.97 IPC G06F 13/00 U.S. Refs 4287562 4641261 4882702 4899306 4967346 Other Refs Motorola Product Preview of MC68HC53 Asynchronous Communication Interface Adapter (ACIA) pp. 3.520-3.523, 1983. Patent Number 5155849 Issue Date 1992 10 13 Appl. Data 338910 1989 04 14 Assignee Xerox Corporation Inventor(s) Westfall, Robert S. Platteter, Dale T. Patterson, Richard K. Smith, Eugene L. Hill, Jr., John R. State/Country NY Title Multilingual operator prompting system which compares language control file version numbers in document and mass memory for changing language files Abstract The method of changing system files to be able to change either the primary or secondary language or both on a rigid disk to another language, and to provide the operator with the option of selecting either the primary or secondary language as the medium for the display messages and prompts by providing the language requirements on a floppy disk, identifying the specific files of the control to be altered to produce the language requirements, loading the floppy disk into a floppy disk drive, and transferring the language requirements to the rigid disk. U.S. Class 395/600 364/DIG1 364/226.4 364/235.7 364/237.2 364/237.82 395/500 395/650 IPC G06F 15/38 U.S. Refs 3979729 4195353 4196450 4231087 4365315 4475806 4484305 4507734 4583194 4665501 4699501 4711560 4730212 4731735 4787050 4809220 4864503 4941249 4999554 Foreign Refs JPX 198608 61-190352 JPX 198608 61-196265 Patent Number 5157620 Issue Date 1992 10 20 Appl. Data 322348 1989 03 13 Assignee International Computers Limited Inventor(s) Shaar, Zakwan State/Country GB3 Title Method for simulating a logic system Abstract A logic simulator has a time loop with a number of time slots into which events are scheduled. The events are wrapped around the loop, so that event times corresponding to different cycles around the loop may be simultaneously present on the loop. This allows a small loop size to be used, which improves performance. Preferably, the loop size is a prime number. If a complete cycle of the loop is made without finding any non-empty slots a jump is made to the next event time, so as to speed up the processing. In one described embodiment, the loop size is static, while in a second described embodiment the loop size is dynamically varied to minimize the insertion of events with different event times into the same slot. U.S. Class 364/578 395/500 IPC G06F 15/16 U.S. Refs 4472789 4677541 4725971 4751637 4901260 Other Refs Abramovici et al.; "A Logic Simulation Machine"; IEEE Tran. CAD of Intog. Circuit and Syst.; Apr. 1983. Howard et al.; "Parallel Processing Interactively Simulates Complex VSLI Logic"; Electronics Dec. 1983. Van Norstrand; "Encyclopedia of Computer Science"; Litton Educational Publishing 1976. Ulrich: Serial/Parallel Event Scheduling for the Simulation of Large Systems, Proceedings of the 1968 ACM National Conference pp. 279-287. Priority GBX 19880531 8812849 Patent Number 5157769 Issue Date 1992 10 20 Appl. Data 860293 1992 03 26 Assignee Traveling Software, Inc. Inventor(s) Eppley, Mark Berg, Lawrence H. Olson, John M. State/Country WA Title Computer data interface for handheld computer transfer to second computer including cable connector circuitry for voltage modification Abstract Disclosed is a computer data interface (6) for connecting a handheld computer (4) and a desktop computer (2). The computer data interface includes a cable (8) having connectors (10 and 12) at each end thereof. Mounted in one of the connectors is an adapter circuit for receiving data signals from the handheld computer and transmitting the signals to the desktop computer at a voltage levels compatible with the desktop computer. Similarly, the adapter circuit receives signals from the desktop computer and transmits the signals to the handheld computer at voltage levels compatible with the handheld computer. The adapter circuit is powered by the desktop computer to prevent draining the batteries of the handheld computer. U.S. Class 395/200 364/DIG1 364/229.1 395/275 395/325 395/500 IPC G06F 13/00 U.S. Refs 4075608 4144565 4217624 4527079 4598410 4602127 4603320 4607170 4631698 4686506 4703198 4739502 4845381 4852041 4853560 4884287 5023824 Other Refs Macintosh, Apple Computer, Inc., 20525 Mariani Ave., Cupertino, CA 95014, pp. 10 & 11, copyright 1983. "Motorola Semiconductor Technical Data", Motorola Telecommunications Device Data, pp. 2-428 to 2-434. "Motorola Semiconductor Technical Data", Motorola, Inc., 1985, one page. Related Data This application is a continuation application based on prior copending application Ser. No. 07/383,215, filed on Jul. 21, 1989 now abandoned. Patent Number 5157778 Issue Date 1992 10 20 Appl. Data 513017 1990 04 23 Assignee Digital Equipment Corporation Inventor(s) Bischoff, Gabriel P. Greenberg, Steven S. State/Country MA Title Method and apparatus for circuit simulation using parallel processors including memory arrangements and matrix decomposition synchronization Abstract A digital data processing system including a plurality of processors processes a program in parallel to load process data into a two-dimensional matrix having a plurality of matrix entries. So that the processors will not have to synchronize loading of process data into particular locations in the matrix, the matrix has a third dimension defining a plurality of memory locations, with each series of locations along the third dimension being associated with one of the matrix entries. Each processor initially loads preliminary process data into a memory location along the third dimension. After that has been completed, each processor generates process data for an entry of the two-dimensional matrix from the preliminary process data in the locations along the third dimension related thereto. Since the processors separately load preliminary process data into different memory locations, along the third dimension, there is no conflict with accessing of memory locations among the various processors during generation of preliminary process data. Further, since the processors can separately generate process data for different matrix entries from the preliminary data, there is no conflict in accessing of the memory locations among the various processors during of the process data. U.S. Class 395/500 364/DIG2 364/750.5 364/931.41 364/933.8 364/937.8 364/966.1 395/800 IPC G06F 7/38 G06F 9/455 G06F 15/16 U.S. Refs T915008 3629843 3903399 4621339 4694411 4694416 4823258 4862347 4888682 Other Refs Jacob et al., "Direct-Method Circuit Simulation Using Multiprocessors", Proceedings of the International Symposium on Circuits & Systems, May 1986, pp. 170-173. Yamamoto et al., "Vectorized LU Decomposition Algorithms for Large Scale Circuit Simulation", IEEE Transactions on Computer Aided Design, vol. Ead-4, No. 3, pp. 232-239, Jul. 1985. Related Data This is a continuation of co-pending application Ser. No. 06/898,476 filed on Aug. 20, 1986, now abandoned. Patent Number 5159679 Issue Date 1992 10 27 Appl. Data 378579 1989 07 10 Assignee Compaq Computer Corporation Inventor(s) Culley, Paul R. State/Country TX Title Computer system with high speed data transfer capabilities Abstract The present invention is a computer system which can perform master unit controlled memory accesses at a first rate, DMA controlled operations at a second rate and burst operations of both types at a higher third rate. The burst operation is set up by performing a standard access cycle, thus setting up the dynamic random access memory row address, and then performing a series of fast, column address-only accesses to the same page of memory. The fast mode must be exited to a standard rate access whenever a page boundary is crossed, with burst operations recommencing thereafter. Wait states can be inserted in all type operations. Thirty-two bit master units can downshift or step down to 16 bit operation to respond to 16 bit burstable responding units. U.S. Class 395/425 395/500 395/550 IPC G06F 12/00 G06F 13/00 U.S. Refs 4479180 4644463 4937734 5034917 5058005 Other Refs IEEE, P1196 Specification-NuBus, Dec. 15, 1986, pp. 1-59. IBM Corp., Personal Computer AT Technical Reference, First Edition, Sep. 1985, pp. 1-24 to 1-38. IBM Corp., RT PC Hardware Technical Reference, vol. 1, Second Edition, Sep. 1986, pp. 6-4 to 6-28. Intel Corporation, Microprocessor and Peripheral Handbook, vol. I, 8237A High Performance Programmable DMA Controller, 1988, pp. 2-234 to 2-252. EISA Press Release, Sep. 13, 1988. The Great Divide, EISA vs. MicroChannel, PC Magazine, Dec. 27, 1988, pp. 165-186. IBM Corp., Personal System/2 Model 80 Technical Reference, First Edition, Apr. 1987, pp. 2-6 to 2-20; 2-77 to 2-113 and 3-15 to 3-27. Compaq Computer Corp., D4 Page DRAM Board Schematics and timing diagrams. EISA vs. MicroChannel: Multimasterin is the key, Electronic Design, Oct. 13, 1988. H. Jessup, PCET 32-Bit Bus Specification, PCET Bus Development Committee, Jun. 9, 1986. M. Vano, Personal Computer Extended Technology Bus Committee Alternate Bus Master Data Multiplexing Draft Subcommittee Report, Jun. 14, 1986. M. Vano, Ambiguities in the IBM PC/RT and PC/AT Documentation (Re: Alternate Bus Masters), Jun. 15, 1986. M. Fung, Extending at Bus Bandwidth, Chips and Technologies, May 21, 1986. Related Data This is a continuation-in-part of copending application Ser. No. 243,480, filed Sep. 9, 1988 now U.S. Pat. No. 5,058,005. Patent Number 5159682 Issue Date 1992 10 27 Appl. Data 426957 1989 10 26 Assignee Matsushita Electric Industrial Co., Ltd. Inventor(s) Toyonaga, Masahiko Akino, Toshiro Okude, Hiroaki State/Country JPX Title System for optimizing a physical organization of elements of an integrated circuit chip through the convergence of a redundancy function Abstract During an optimization of an organization of mutually-related elements, an element organization is gradually changed toward an objective specification by local changes of the element organization. A value of an objective function depends on a degree of a nearness of the element organization to the objective specification. A redundancy function of a number of elements in an improvement group is determined in consideration of a fluctuation in the value of the objective function, so that suitable changes of the improvement group are performed by use of the definite redundancy. An intermediate element organization is rejected and accepted in accordance with the redundancy function value, so that a final element organization can be obtained in consideration of a global aspect of the element organization. U.S. Class 395/500 364/DIG1 364/DIG2 364/148 364/232.3 364/491 364/933.8 IPC G06F 9/44 U.S. Refs 3654615 3681782 4495559 4615011 4630219 4754408 4931944 4964057 Other Refs IEEE Journal of Solid-State circuits, vol. SC-20, No. 2, Apr. 1985, New York US pp. 510-522; Sechen et al: `the timberwolf placement and routing package` *p. 510, column 2, line 33-p. 512, column 2, line 31**p. 513, column 1, line 26-p. 514, column 2, line 8*. Science, vol. 200, No. 4598, May 13, 1983, pp. 671-680; Kirkpatrick et al: `optimization by simulated annealing`. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. CAD-6, No. 2, Mar. 1987, New York US pp. 211-221; Siarry et al: `Thermodynamic Optimization of Block Placement`. Priority JPX 19881028 63-273433 Patent Number 5159683 Issue Date 1992 10 27 Appl. Data 405041 1989 09 08 Assignee Western Digital Corporation Inventor(s) Lvovsky, Lazar Lushtak, Alexander S. State/Country CA Title Graphics controller adapted to automatically sense the type of connected video monitor and configure the control and display signals supplied to the monitor accordingly Abstract An automatic monitor sensing graphics controller for use with a computer and a display monitor. The display monitor has a specific capability. The controller, mounted within the computer, comprises a plurality of signal lines, a buffer device connected to both the signal lines and the computer, a connector device connected to both the signal lines and the display monitor, and an automatic monitor sensing unit connected to the signal lines for sensing and determining the capability of the display monitor. U.S. Class 395/500 364/DIG2 364/921.9 364/926.9 364/927.2 364/929.4 395/100 IPC G05F 3/14 U.S. Refs 3676858 4079452 4218740 4342029 4403303 4500933 4575714 4607379 4631698 4641262 4647912 4670855 4698770 4707803 4788657 4852041 4918436 4964038 Other Refs Advertisement, PC Magazine, p. 111, vol. 7, No. 7, Apr. 12, 1988. "EGA, VGA Are the Best for Color Display," The Recorder, p. 12, Jul. 5, 1988, Barry D. Bayer and Mark J. Welch. IBM Enhanced Graphics Adapter (1984). Related Data This application is a continuation, of application Ser. No. 891,545, filed Jul. 29, 1986 now abandoned. Patent Number 5159684 Issue Date 1992 10 27 Appl. Data 356973 1989 05 24 Assignee Pitney Bowes Inc. Inventor(s) Kroll, Paul Gerety, Eugene P. Holtz, Earl B. State/Country CT Title Data communication interface integrated circuit with data-echoing and non-echoing communication modes Abstract An integrated circuit communication interface device includes data bus terminals, a serial output terminal, a serial input terminal, and an internal data bus. A data bus buffer connects the data bus terminals to the internal data bus. A transmit buffer connects the serial output terminal to the internal data bus. A receive buffer connects the serial input terminal to the internal data bus. Control circuitry controls the buffer so that the device receives or transmits data in either the Echoplex protocol or the RS 232 protocol. The device includes a data register which is programmed to select the device's mode of operation. U.S. Class 395/500 364/DIG1 364/239.9 364/240.9 364/242.5 371/34 IPC G06F 11/00 U.S. Refs 3228000 3680045 3805234 4070648 4346440 4347608 4377862 4673976 4852127 5051899 Foreign Refs GBX 197106 1236386 Other Refs Maiwald et al., "Error Recovery in Data Transmission", IBM Technical Disclosure Bulletin, vol. 13, No. 10, Mar. 1971. Intel, MCS-8080/8085 Family User's Manual, 1986, pp. 6-49 to 6-65. Patent Number 5161116 Issue Date 1992 11 03 Appl. Data 316375 1989 02 27 Assignee Dynix Inventor(s) Schneider, J. Wayne Richan, K. Brook Wilson, Richard K. State/Country UT Title System for evaluating the performance of a large scale programmable machine capable of having a plurality of terminals attached thereto Abstract A robot system for evaluating the performance of a host computer system which has a plurality of host communication ports connectable to a corresponding plurality of user terminals. Prior to placing the host computer system into service with the user terminals, the robot system is used to emulate the user terminals and to emulate predefined computing tasks input to the host computer system for the user terminals. The master CPU in turn is connected to the plurality of smaller slave CPU's. The smaller slave CPU's are connected to the communication ports of the host computer system. Each of the slave CPU's emulate several user terminals by inputting various computing tasks to the host computer system. Input of the computing tasks to the host computer system by the slaves CPU's is coordinated at the terminal of the master CPU by a single operator, who also monitors at that terminal the host computer system's elapsed time for performing each computing tasks so as to thereby assess the performance of the host computer system. U.S. Class 364/551.01 395/500 IPC G06F 15/20 U.S. Refs 4091448 4377852 4516216 4802164 4849879 5062055 Other Refs Aug. 1979 Federal Procurement Request RTE Log Analyses. Patent Number 5161222 Issue Date 1992 11 03 Appl. Data 569857 1990 08 20 Assignee Human Microprocessing, Inc. Inventor(s) Montejo, Leopoldo S. Pean, Martine State/Country FRX Title Software engine having an adaptable driver for interpreting variables produced by a plurality of sensors Abstract A method for interpreting variables produced by a sensor which communicates by a means of serial analog protocols including interpreting an external process request for data information from the sensor; overlaying a predetermined adaptable driver which when adjusted in a predetermined fashion corresponds to the characteristics of the sensor; polling or listening to the sensor thereby receiving the data information requested; and transmitting the information to a predetermined destination. U.S. Class 395/500 364/DIG2 364/934 364/934.2 364/934.3 364/935.42 364/940.1 364/940.9 364/942.8 IPC G06F 13/14 U.S. Refs 4481574 4570217 4589063 4649479 4663704 4672532 4701848 4734854 4858101 5014185 Other Refs Armbrust et al., "Forward Looking DVI," PC Tech Journal, vol. 3, No. 9, Sep. 1985, pp. 42-55. Patent Number 5161232 Issue Date 1992 11 03 Appl. Data 850214 1992 03 12 Inventor(s) Beran, James T. State/Country CA Title Modular self-programmer Abstract A self-programming technique includes receiving a sequence of input signals and comparing each input signal with an expectation signal. A sequence of output signals is generated from the input signals, and at least part of the output signal sequence is stored when the expectation signal compares favorably with the input signal. Modular units performing this technique may be connected as a master with one or more servants. The master provides the expectation signals for the servants as its output and receives their signals indicating their comparison outcomes as its input. Within each programmer, a random number may be generated as an output when the input signal received is not expected and has not previously been stored as an input preceding an output signal. The random number output provides trial and error capabilities. U.S. Class 395/800 364/DIG2 364/916.2 364/972.2 395/50 395/500 IPC G06F 15/00 U.S. Refs 3601811 3716840 4258425 4366551 4384273 4479241 4484303 4516202 4523299 4578764 4599693 4633385 4638421 4697242 4773028 4783741 Foreign Refs EPX 198510 0159463 WOX 198503 85-01364 Other Refs Narendra, K. S. and Thathachar, M. A. L., "Learning Automata-A Survey," IEEE Transactions on Systems, Man, and Cybernetics, vol. SMC-4, No. 4, Jul. 1974, pp. 323-334. Laird, J. E., Rosenbloom, P. S., Newell, A., "Towards Chunking as a General Learning Mechanism" in Two Soar Studies, (Pittsburgh: Carnegie-Mellon) 1985. Rosenbloom, P. S., Laird, J. E., Newell, A., Golding, A., Unruh, A. "Current Research on Learning in Soar" May 1985. Marrs, T. The Personal Robot Book, (Blue Ridge Summit: TAB Books) 1985, pp. 44-51. Holusha, J., "Robots That See and Feel", The New York Times, Jun. 6, 1985, p. D2. Interrante, L. D., and Biegel, J. E. "The Marriage of Artificial Intelligence and Robotics in the Manufacturing Environment", Robots 9 Proc., Jun. 1985. Heiserman, D. L. Robot Intelligence . . . With Experiments, (Blue Ridge Summit: TAB Books) 1981, pp. 13-23, 31-50, 61-66, 91-105, 140-159, and 219-290. Heiserman, D. L. How to Build Your Own Self-Programming Robot, (Blue Ridge Summit: TAB Books) 1979, pp. 9-19 and 175-218. Yarmolinsky, M., "On Impossibility in Biology," in Davis, P. J. and Park, D., Eds., No Way, W. H. Freeman and Co., New York, 1987, pp. 29-43. Related Data This is a continuation of application Ser. No. 06/776,819, filed Sep. 17, 1985 now abandoned. Patent Number 5163016 Issue Date 1992 11 10 Appl. Data 489438 1990 03 06 Assignee AT&T Bell Laboratories Inventor(s) Har'El, Zvi Kurshan, Robert P. State/Country ILX Title Analytical development and verification of control-intensive systems Abstract Designs are created through a high-level to low-level transformation in the form of a formal top-down development procedure based upon successive refinement. Starting with a high-level (abstract) model, such as a formal abstraction of a protocol standard, successively more detailed models are created through successive refinement, in a fashion which guarantees that properties verified at one level of abstraction hold in all successive levels of abstraction. The successive refinements end with a low-level "model" which forms the ultimate implementation of the protocol. In one embodiment of this invention, the analysis/development apparatus creates a unique C language code representation of the specified system that is guaranteed to carry out the tasks specified when executed in a stored program controlled machine. In another embodiment, the code is used to create a "net list" for manufacturing the specified system. U.S. Class 364/578 395/500 IPC G06F 15/20 U.S. Refs 4587625 4694411 4862347 4907180 4965758 Other Refs R. P. Kurshan in Reducibility on Analysis of Coordination, published in Lecture Notes in Computer Science (LNICS) 103 titled Discreet Event Systems: Models and Applications, Springer-Verlag, pp. 19-39 (1987). K. G. Larsen et al., in Lecture Notes in Computer Science, Springer-Verlag, 14th International Colloquium Karlsruhe, Fed. Rep. of Germ. Jul. 13-17, 1987. J. E. Hopcroft in An n log n Algorithm for Minimizing the States in a Finite Automaton, Theory of Machines and Computations (Kohavi, Paz, eds.) Academic Press, pp. 189-196. Van Nostrand; "Sequential Machines"; 1983. Dowsing; "Simulating hardware Structure in OCCAM"; Software and Microsystems vol. 4, No. 4 Aug. 1985. Patent Number 5163145 Issue Date 1992 11 10 Appl. Data 343102 1989 04 25 Assignee Dell USA L.P. Inventor(s) Parks, Terry J. State/Country TX Title Circuit for determining between a first or second type CPU at reset by examining upper M bits of initial memory reference Abstract A computer system provides a RESET-signal for resetting registers upon start-up of the system, and includes a central processor unit (CPU) of an optional type and a detect circuit for determining which optional type. On start-up, the CPU sends out an initial memory reference at the highest possible address. The first type of CPU has a memory address register of N bits. The memory address register of the second type of CPU has a memory address register of N+M bits. The upper M bits input to the memory address register of the first type of CPU are grounded. A detect circuit is activated by the CPU addressing memory and receives at least one of the M upper bits. If that bit is not grounded, then the CPU is of the second type and, if grounded, it is of the first type. The RESET-signal upon start-up assures that the detect circuit will be activated on start-up. U.S. Class 395/500 364/DIG2 364/929.5 364/933.2 364/949.4 395/800 IPC G06F 1/24 U.S. Refs 4070704 4167781 4315308 4432067 4592011 4641261 4654789 4667305 4677548 4727477 4766538 4866664 4885482 4967346 4987529 4991085 Other Refs MC68881/MC68882 Floating-Point Coprocessor User's Manual, Motorola Inc., Prentice Hall, section 10-1. Patent Number 5164911 Issue Date 1992 11 17 Appl. Data 451208 1989 12 15 Assignee Hewlett-Packard Company Inventor(s) Juran, Michael T. Von Bank, David G. State/Country CO Title Schematic capture method having different model couplers for model types for changing the definition of the schematic based upon model type selection Abstract Disclosed is a schematic capture and design verification system wherein the graphic symbol linked to a component is separated from the model used to simulate the component. Each component has a graphics symbol linked to a link or scion page. The link page also contains a list of all models that can be used with the component. The system allows a model to be selected for each component in a schematic, and allows the model to be changed at any time. The system also allows the models for all components to be changed with a single command. The user enters a schematic into the system, then selects a model for each component used in the schematic. After a model has been selected for each component, the user requests the system to build a netlist that describes the schematic to a simulator or other analysis or synthesis tool. In building the netlist, parameters are extracted from the link page for each component and included in the netlist to be used by the simulator. When a different simulation is desired by the user, the user instructs the system to change the model linked to the components to a new model suitable to the second simulator. The system then builds a new netlist, using parameters specific to the new model and the second simulator. U.S. Class 364/578 364/DIG2 364/275.6 364/488 364/917.96 395/100 395/500 IPC G06F 15/60 G06F 15/20 U.S. Refs 3846763 4703435 4827427 4954953 5050091 5051938 5095441 Patent Number 5165030 Issue Date 1992 11 17 Appl. Data 321931 1989 03 10 Assignee International Business Machines Corporation Inventor(s) Barker, Barbara A. State/Country TX Title Method and system for dynamic creation of data stream based upon system parameters and operator selections Abstract A method for the dynamic creation of a data stream of continuous data elements for transmission by a data processing system. One or more data stream libraries are created within external or "in-line" storage facilities for utilization by the data stream build process and a plurality of data resources are stored therein. Data stream resources may include: data stream templates; environments; page structures; formatting descriptions; and, object data. Object data may include: text; image; graphics; font specifications; color tables; and, code page specifications. The data stream build process then prompts the operator for inputs which specify desired data stream characteristics. A plurality of options are then presented to the operator based upon the operator's inputs and selected data processing system parameters which are utilized in a heuristic manner as determined by system parameters. A data stream is then dynamically created from selected resources stored within the data stream libraries or created in response to selections by the operator from the plurality of options presented by the dynamic build process. U.S. Class 395/500 364/DIG1 364/DIG2 364/231 364/231.31 364/234.3 364/234.4 364/237.2 364/242.5 364/242.94 364/242.95 364/242.96 364/280 364/280.7 364/281.6 364/281.7 364/283.3 364/284.4 364/286 364/286.1 364/286.2 364/286.3 364/419 IPC G06F 3/14 G06F 15/403 G06F 9/06 G06F 15/40 U.S. Refs 4156798 4463442 4500960 4583161 4586158 4648061 4723209 4783739 4805134 4829470 4831552 4937036 4962475 Patent Number 5167021 Issue Date 1992 11 24 Appl. Data 246249 1988 09 19 Assignee NCR Corporation Inventor(s) Needham, David B. State/Country FL Title Multimedia interface device and method Abstract An interface device between, and a method for providing data from, one of a plurality of optical or magnetic media reader devices to a host is disclosed. The interface device comprises first and second input ports, each port being connectable to a selected media device. The device also comprises means for automatically identifying the type of media device connected to each of the ports by sequentially sampling control or data signals therefrom. It also includes means for determining when an identified media device is active by sampling control or data signals from each port that has an identified media device connected thereto. U.S. Class 395/275 364/DIG2 395/500 395/800 IPC G06F 15/20 U.S. Refs Re31692 3876981 4029944 4041279 4056712 4180207 4266281 4322794 4371925 4396995 4434460 4442504 4809217 4821179 Patent Number 5167023 Issue Date 1992 11 24 Appl. Data 625780 1990 12 07 Assignee International Business Machines Inventor(s) de Nicolas, Arturo M. O'Quin, III, John C. State/Country TX Title Translating a dynamic transfer control instruction address in a simulated CPU processor Abstract The system and method of this invention simulates the flow of control of an application program targeted for a specific instruction set of a specific processor by utilizing a simulator running on a second processing system having a second processor with a different instruction set. The simulator reduces the number of translated instructions needed to simulate the flow of control of the first processor instructions when translating the address of the next executable instruction resulting from a dynamic transfer of control, i.e., resulting from a return instruction. The simulator compares the address that is loaded at run time by the return instruction with the return address previously executed by that instruction. If the last return address matches, the location of the return is the same. If the last return does not match, a translate look-aside buffer is used to determine the address. If the translate look-aside buffer does not find the address, then a binary tree look up mechanism is used to determine the address of the next instruction after a return. The performance of the simulator is enhanced by utilizing the easiest approaches first in the chance that a translated instruction will result most efficiently. U.S. Class 395/375 364/DIG1 364/232.3 364/247 364/247.6 364/247.7 364/262.4 364/262.9 395/500 IPC G06F 9/30 U.S. Refs 4347565 4370709 4587612 4638423 4700291 4727484 4841476 Foreign Refs EPX 198704 0217068 Other Refs K. J. McNeley et al., "Emulating a Complex Instruction Set Computer with a Reduced Instruction Set Computer", IEEE Micro, Feb., 1987, vol. 7, No. 1, pp. 60-71. Graham, C., "Amiga's Trump Card: IBM PC Emulation", AmigaWorld, vol. 1, No. 2, Nov./Dec., 1985, pp. 34-35. "SoftPC", Insignia Solutions, Inc., ISI Soft PC Data Sheet Rev., 3.0, Jan. 87, 8 pages. Warner, E., "Unix-Based Workstations to Run DOS", Info World, Jul. 6, 1987, p. 8. May, C., "Mimic: A Fast System/370 Simulator", SIGPLAN, 1987, Proceedings of the ACM SIGPLAN '87 Symposium on Interpreters and Interpretive Techniques, Jun. 87, pp. 1-13. Related Data This is a continuation of application Ser. No. 07/151,137, filed Feb. 1, 1988, now abandoned. Patent Number 5168441 Issue Date 1992 12 01 Appl. Data 531261 1990 05 30 Assignee Allen-Bradley Company, Inc. Inventor(s) Onarheim, William G. Dudley, Horace Meyer, Barbara E. Viste, Michael J. Morley, David J. State/Country WI Title Methods for set up and programming of machine and process controllers Abstract Graphical editing methods are employed to construct programs in high-level graphical languages prior to compilation and operation in controllers for industrial or commercial equipment. The editing methods include process, hardware and program editing tasks for defining both process and hardware I/O points and connecting them to variables in a controller program. Each editing task has a tree graph window, a graph editing window, and a palette with rotating panels of graphical editing tools. The hardware editing taks uses two-layered icons to graphically simulate the hardware environment. A plurality of graph types are based on generalized node-vert-arc graphical elements which are special classes programmed in the Smalltalk programming language. Languages for the controller program include function block, sequential function chart and ladder diagram. U.S. Class 364/146 364/188 364/192 395/500 IPC G06F 15/46 G06F 15/60 U.S. Refs Re32632 4315315 4570217 4663704 4736340 4742443 4827404 4870561 4885694 4901221 4939507 5005119 5021976 5079723 Foreign Refs EPX 198606 0184422 DEX 199011 4013960 GBX 199101 2233128 Other Refs Ambler and Burnett, "Influence of Visual Technology on the Evolution of Language Environments", Computer, IEEE Oct., 1989, pp. 9-22. Kramer, Magee & Ng, "Graphical Configuration Programming", Computer, IEEE Oct., 1989, pp. 53-65. Smalltalk V/286 Tutorial and Programming Handbook, Digitalk Inc., 1988, pp. 1-3. Miller, R., "Savior: The Object Is Cell Control", Managing Automation, Apr. 1988, pp. 66-70. Flexis.TM. ToolSet.TM. Brochure, Savoir Systems Group, Oakland, Calif., Oct., 1987. Flexis.TM. Product Overview, Savoir Systems Group, Oakland, Calif., Apr., 1988. Draft of Approved French Standard, Sep. 1981. International Electrotechnical Commission--Preparation of Function Charts for Control Systems, Jan. 1982. International Electrotechnical Commission--Standard for Programmable Controllers--Part 3: Programming Languages, Nov. 1984. "Programmable Controller Functions Are Enhanced by Structural Programming", Control Engineering, Feb. 1984. "A Program Development Tool for the Entire Automation Staff", published by Siemens, date unknown. "Controller Combines Computer and Programmable Control Functions", Control Engineering, Nov. 1984. "Data PCs From Maxitron--Conceptual and Technical Perspectives" brochure published in 1985. P. Liu, et al., "A Layered Intelligence Architecture for Programmable Controller Configurations", ESD/SMI Expert Systems, Proceedings, Dearborn, Mich., Jun. 9-11, 1987. D. Ingalls, et al., "Fabrik, A Visual Programming Environment" OOPSLA '88 Proceedings, Sep. 25-30, 1988. Patent Number 5168559 Issue Date 1992 12 01 Appl. Data 337756 1989 04 13 Assignee NEC Corporation Inventor(s) Tamura, Toshinori State/Country JPX Title Emulation system capable of complying with microcomputers having different on-chip memory capacities Abstract An emulation system which includes an evaluation chip, a program memory and a data memory and is coupled to an external memory comprises an area discriminator for discriminating whether or not a location to be accessed by the evaluation chip is within an on-chip area of a target microcomputer and notifying the evaluation chip of the result of discrimination. On the basis of the result of discrimination, the evaluation chip operates to access the data memory when the space to be accessed by the evaluation chip is within the on-chip area of the target microcomputer and the external memory when the space to be accessed by the evaluation chip is not within the on-chip area of the target microcomputer. U.S. Class 395/425 364/DIG1 364/232.3 364/243 364/254.4 395/500 IPC G06F 12/00 G06F 9/455 U.S. Refs 4434462 4450519 4450524 4514805 4571676 Priority JPX 19880413 63-92076 Patent Number 5168562 Issue Date 1992 12 01 Appl. Data 313236 1989 02 21 Assignee Compaq Computer Corporation Inventor(s) Estepp, Craig A. Burckhartt, David M. State/Country TX Title Method and apparatus for determining the allowable data path width of a device in a computer system to avoid interference with other devices Abstract A circuit board is capable of indicating whether it is located in an 8 bit slot and is capable of operating on an 8 bit or 16 bit wide data path. The user can indicate the desired operating data width. Based on determinations of slot size, desired operating width and the presence of other 8 or 16 bit devices, the operating data path width is automatically set. Warnings are given for selected operating conditions. U.S. Class 395/500 364/DIG2 364/232.8 364/240 364/240.3 364/927.92 364/931 364/931.1 364/935.47 395/325 IPC G06F 13/40 G06F 13/00 U.S. Refs 4213177 4286321 4447878 4633437 4679166 4683534 4716527 4736317 4766538 4831514 4845611 4876639 4893235 4965723 Other Refs IBM Corp., RT PC Hardware Technical Reference, vol. 1, Second Edition, Sep. 1986, pp. 6-4 to 6-28. IBM Corp., Personal Computer AT Technical Ref., First Edition, Sep. 1985, pp. 1-24 to 1-38. Patent Number 5168563 Issue Date 1992 12 01 Appl. Data 859290 1992 03 25 Assignee Hewlett-Packard Company Inventor(s) Shenoy, Anil K. D'Angelo, Vincent Utz, Jr., Walter J. State/Country CA Title Various possible execution paths measurement and analysis system for evaluating before writing source codes the efficiency performance of software designs Abstract A software engineering tool is disclosed which enables the efficiency and performance of a program design to be evaluated prior to the time the program is written into code. Every possible path that can be followed in the implementation of the program is identified, and its length is measured. From this information, reports are generated which point out the longest paths in the program and sources of potential performance problems. In addition, weights which identify relative complexities or performance timings can be assigned to individual modules in the program, and form the basis of other reports which indicate timing performance. The user is provided with the opportunity to alter the weights assigned to modules, and thereby determine the effect which different weights have on the overall performance of the program. U.S. Class 395/500 364/DIG1 364/275.6 364/488 364/578 395/575 395/800 IPC G06F 15/60 G06F 15/20 U.S. Refs 3702005 4742467 4782461 4809170 4845665 4864569 Other Refs Stucki; "A Case for Software Testing"; IEEE Transactions on Software Engineering, vol. SE-2, No. 3, Sep. 1976 p. 194. Hakozaki et al., "Design and Evaluation System for Computer Architecture"; AFIPS Conference Proceeding; vol. 42, pp. 81-86, 1973. Nejmeh; "NPath: A measure of Execution Path Complexity and its Applications"; Communications of ACM; Feb. 1988; vol. 31, No. 2; pp. 188-200. K. Soule; "Algorith for Tracing Execution Paths to a Given Location in a Program"; IBM Technical Disclosure Bulletin; vol. 14 No. 4; Sep. 1971; pp. 1016-1019. Antoine et al.; "Effective Software Debugging Using a Program Trace"; Electrical Communication; vol. 54, No. 2, 1979; pp. 111-114. Feingold; "Computer System Simulation: A Design Evaluation Tool"; Winter Simulation Conference; Dec. 6-8, 1976; pp. 293-308. Merle et al.; "A Tool for the Aided Design and Evaluation of Computer Architectures"; IEEE 1978; pp. 128-135. Yang et al., "Critical Path Analysis for the Execution of Parallel and Distributed Program"; Conference location San Jose, Calif., date 13-17 Jun. 1988; pp. 366-373. Proceedings of the Eight Annual International Phoenix Conference on Computers and Communications, Mar. 24, 1989, Scottsdale, Ariz., pp. 332-336 Jianping Wang et al.: "Software Performance Analysis Using a Graphic Modeling Technique". Hewlett-Packard Journal, No. 4, Aug. 1988, Palo Alto, Calif. USA, pp. 71-82, James P. Ambras et al., "Microscope: An Integrated Program Analysis Toolset". Proceedings of the 10th International Conference on Software Engineering, Apr. 15, 1988, Singapore, pp. 388-395, James L. Benjamin, "Pilot: A Prescription for Program Performance Measurement". Related Data This is a continuation of copending application Ser. No. 07/331,315 filed on Mar. 29, 1989, now abandoned. Patent Number 5173869 Issue Date 1992 12 22 Appl. Data 629964 1990 12 21 Assignee Mazda Motor Corporation Inventor(s) Sakamoto, Shunji Hoshino, Toshihiko State/Country JPX Title Method of simulating a sequential control for analyzing a production line in a production system Abstract A method of simulating a sequential control program by composing simulation ladder program elements with timer elements which correspond to the ladder program elements of the sequential control program. If the operations of a plurality of operation steps are performed in parallel with each other, a time chart is prepared by considering the parallel relationships between the operation steps, and simulation elements are thereafter formed in execution order in accordance with the timing chart. U.S. Class 364/578 364/147 395/500 IPC G06F 15/20 G05B 9/02 U.S. Refs 4149235 4167788 4247901 4455619 4742443 4858101 4991076 Foreign Refs EPX 198303 0092312 EPX 198508 0177164 DEX 197912 148264 DEX 198408 3430971A1 JPX 198805 63-106004 JPX 198906 1-28962 JPX 199004 0098706 JPX 199011 2-84205 GBX 197204 1383093 Priority JPX 19891225 1-335271 JPX 19900928 2-260143 Patent Number 5175817 Issue Date 1992 12 29 Appl. Data 439239 1989 11 20 Assignee Digital Equipment Corporation Inventor(s) Adams, Samuel T. Kaycee, Mahendra J. Heffler, Michael J. State/Country NH Title Data representation protocol for communications between different networks Abstract A data representation and protocol are provided to interface two networks. A plurality of information units to be transmitted from one network to another are formatted into a variable size block in accordance with the protocol. Each block contains a header field storing a total information unit count and a control information unit count. The remainder of the block stores the actual information itself, both control and data, in consecutive byte locations, with the actual control information located at the end of the block. The block can then be sent to another network for processing. A device in the other network need only reference the block header to determine whether the information contained in the block is control or data. This speeds the processing of large quantities of either all data information and/or control information. U.S. Class 395/200 364/DIG1 364/228 364/240.8 364/242.94 364/242.95 364/284 364/284.4 395/500 IPC G06F 13/38 G06F 15/16 G06F 5/00 U.S. Refs 4475192 4493021 4494194 4511958 4554659 4631666 4644547 4791566 4800488 4814980 4823122 4868742 4873626 Foreign Refs EPX 198601 0167725 Other Refs F. Halsall, "Data Communications, Computer Networks and OSI", Addison-Wesley Co., 1988. Patent Number 5175819 Issue Date 1992 12 29 Appl. Data 500678 1990 03 28 Assignee Integrated Device Technology, Inc. Inventor(s) Le Ngoc, Danh Au, Fulam Mick, John R. State/Country CA Title Cascadable parallel to serial converter using tap shift registers and data shift registers while receiving input data from FIFO buffer Abstract A parallel-to-serial FIFO buffer device (100) employs a FIFO buffer (110) for storing words of data; a tap-shift-register portion (112); and a data-shift-register portion (116) for converting from parallel to serial format words of data stored in the FIFO buffer (110), tap-shift-register portion (112) controls the conversion process, receives (150) a serial-input-expansion (RSIX) input signal, and develops (170) a serial-output-expansion (RSOX) output signal. The serial-input-expansion input signal (150) and the serial-output-expansion output signal (170) permit the device (100) to be connected with one, or more, similar, device(s) for word length and/or depth expansion. U.S. Class 395/250 341/101 364/DIG1 364/238.7 364/239.2 364/926.2 364/926.5 364/939.5 364/951 395/500 IPC G06F 5/00 U.S. Refs 4218758 4298936 4377806 4497041 4750149 4907186 5055842 5089819 Patent Number 5175843 Issue Date 1992 12 29 Appl. Data 428808 1989 10 30 Assignee General Electric Company Inventor(s) Casavant, Albert E. Hartley, Richard I. State/Country NY Title Computer-aided design method for restructuring computational networks to minimize shimming delays Abstract A computer-aided design method for restructuring computational networks to minimize latency and shim delay, suitable for use by a silicon compiler. Data-flow graphs for computational networks which use trees of operators, each performing associative and commutative combining of its respective imput operands to generate a respective output operand, are converted to data-flow graphs with multiple-input operators. Data-flow graphs with multiple-input operators, after being optimally scheduled, are converted to data-flow graphs which use trees of dual-input operators or of dual-input and three-input operators, those trees having minimum latency and shim delay associated with them. These data-flow graphs then have shim delay minimized in them, e.g. by being subjected to linear programming. U.S. Class 395/500 364/DIG1 364/259 364/259.1 364/271.5 IPC G06F 9/00 U.S. Refs 3978452 4447875 4654780 4734848 4827428 4942396 4956773 Patent Number 5175859 Issue Date 1992 12 29 Appl. Data 517293 1990 05 01 Assignee Integrated Device Technology, Inc. Inventor(s) Miller, Michael J. Bourekas, Philip A. Willenz, Avigdor State/Country CA Title Apparatus for disabling unused cache tag input/output pins during processor reset by sensing pull-down resistors connected to disabled pins Abstract A method of programming a cache tag comparator by designing a semiconductor device's internal circuitry such that an input/output pin of the device may be programmed by an external resistor to ground that will indicate during the reset phase of the device that an alternate function for the pin is to be selected or that the pin itself is to be disabled. U.S. Class 395/800 307/465 364/DIG1 364/260.8 364/280.2 395/500 IPC G06F 1/22 U.S. Refs 4432049 4987319 5051622